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19-3732; Rev 1; 8/06
KIT ATION EVALU ABLE AVAIL
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
General Description
The MAX9851/MAX9853 are single-chip, stereo audio CODECs designed to provide a complete audio solution for a GSM/GPRS/EDGE cell phone. The MAX9851/ MAX9853 provide stereo DirectDriveTM headphone amplifiers, a mono receiver speaker amplifier, stereo Class D speaker amplifiers (MAX9851 only), stereo differential line outputs (MAX9853 only), microphone input amplifiers, plus flexible input selection and gain control. Two serial digital audio interfaces are included, one intended to accept voiceband data and the other accepting I2S data. The voiceband interface can be reconfigured as needed to act as a secondary I2S feed input--allowing multiple audio source mixing of ringer tones or other audio at different sample rates. A transducer/vibrator signal can be derived from digital audio. The stereo digital-to-analog converter (DAC) path includes filtering and mixing, programmable-gain amplifiers (PGA), soft muting, and optional voiceband digital filtering. The MAX9851/MAX9853 accept up to two digital audio inputs at different sample rates. All analog inputs have PGAs on the front end, allowing dynamic range optimization with a wide range of input sources. The stereo analog-to-digital converter (ADC) converts audio signals from either internal or external microphones or stereo line inputs. The microphone amplifiers have a programmable gain from 0 to 40dB to handle both amplified microphones and electret modules. In addition to a digital highpass filter to remove DC offset voltages, the ADC also features voiceband digital filtering. The digital audio interfaces support a variety of serial audio formats. The secondary serial audio interface has an independent supply voltage to allow integration into multiple supply systems. Control for volume levels, signal mixing, and operating modes is done through the I2C 2-wire interface. All circuitry is optimized for high PSRR. The MAX9851/ MAX9853 use a thermally efficient, space-saving 48-pin thin QFN package (7mm x 7mm x 0.8mm) with an exposed pad.
Features
o +1.7V to +3.3V (Digital) and +2.6V to +3.3V (Analog) Operation o +2.6V to +5.5V Class D Speaker Amplifier Operation (Direct from Battery) o Low 26mW Quiescent Power Consumption (Playback) o High 98dB Power-Supply Rejection Ratio o 8kHz to 48kHz Sample Rate (Replay and Record) o Stereo 18-Bit ADC and DAC o Low-Noise Stereo Microphone Inputs and Stereo Line Inputs o Dual Source Digital Mixing (DAC) o Selectable Voiceband Filter for Recording/Playback Modes o Digital Filtering, Soft Mute, and Volume Control o Low-Noise, High-PSRR Microphone Bias Generator o Stereo DirectDrive Headphone Amplifier (2 x 50mW) o Mono DirectDrive Handset Receiver Amplifier (1 x 105mW) o Stereo Class D, Ultra-Low-EMI, Filterless Speaker Amplifier with Active Emissions Limiting (2 x 1.25W, 8) (MAX9851) o Stereo Differential Line Output Amplifiers (MAX9853) o Clickless/Popless Operation o Flexible Shutdown Modes for Power Saving o Comprehensive Headset Detection o Ultra-Low Power Wake-Up on Headset Detection
MAX9851/MAX9853
Ordering Information
PART MAX9851ETM+ MAX9853ETM+ PIN-PACKAGE 48 TQFN-EP** (7mm x 7mm x 0.8mm) 48 TQFN-EP** (7mm x 7mm x 0.8mm) PKG CODE T4877-6 T4877-6
Applications
GSM/GPRS/EDGE Cell Phones PDAs/SmartPhones
Note: All devices specified over the -40C to +85C temperature range. +Denotes lead-free package. **EP = Exposed pad. Pin Configurations and Selector Guide appear at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Simplified Block Diagrams
DVDD AND DVDDS2 1.7V TO 3.3V AVDD AND CPVDD 2.6V TO 3.3V PVDD 2.6V TO 5.5V
MAX9851
SDOUTS1 SDINS1 BCLKS1 LRCLKS1 DAC DIGITAL INTERFACE 1 DIGITAL FILTERING AND MIXERS DIGITAL INTERFACE 2 ADC ADC RIGHT SPEAKER INTERNAL MICROPHONE SDA SCL I2C VIBRATOR CONTROLLER MONO RECEIVER SPEAKER ANALOG MIXERS LEFT SPEAKER
DAC
SDOUTS2 SDINS2 BCLKS2 LRCLKS2
LEFT EXT MICROPHONE
RIGHT EXT MICROPHONE
LINEIN INTERNAL TRANSDUCER/VIBRATOR
LINEIN
DVDD AND DVDDS2 1.7V TO 3.3V
AVDD AND CPVDD 2.6V TO 3.3V
MAX9853
SDOUTS1 SDINS1 BCLKS1 LRCLKS1 DAC DIGITAL INTERFACE 1 DIGITAL FILTERING AND MIXERS DIGITAL INTERFACE 2 ADC ADC RIGHT LINE OUT INTERNAL MICROPHONE SDA SCL I2C VIBRATOR CONTROLLER MONO RECEIVER SPEAKER ANALOG MIXERS LEFT LINE OUT
DAC
SDOUTS2 SDINS2 BCLKS2 LRCLKS2
LEFT EXT MICROPHONE
RIGHT EXT MICROPHONE
LINEIN INTERNAL TRANSDUCER/VIBRATOR
LINEIN
2
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ABSOLUTE MAXIMUM RATINGS
(Voltages with respect to AGND) AVDD, DVDD, DVDDS2, CPVDD .................................-0.3V to +4V PVSS, SVSS ...............................................................-4V to +0.3V PVDD .........................................................................-0.3V to +6V AGND, DGND, CPGND, PGND.............................-0.3V to +0.3V HPL, HPR, REC ...........................(SVSS - 0.3V) to (AVDD + 0.3V) LSPK+, LSPK-, RSPK+, RSPK- ................-0.3V to (PVDD + 0.3V) LINEIN1, LINEIN2........................................................-2V to +2V EXTMICBIASL, EXTMICBIASR.................-0.3V to (AVDD + 0.3V) INTMICP, INTMICN, EXTMICL, EXTMICR ...................-2V to +2V EXTMICGND..........................................................-0.3V to +0.3V C1N..........................................(PVSS - 0.3V) to (CPGND + 0.3V) C1P.......................................(CPGND - 0.3V) to (CPVDD + 0.3V) PREG, REF, MBIAS, INTMICBIAS............-0.3V to (AVDD + 0.3V) NREG ........................................................+0.3V to (SVSS - 0.3V) OUTL+, OUTL-, OUTR+, OUTR-, FAULTIN................................................-0.3V to (AVCC + 0.3V) MCLK, IRQ, VIBE, SCL, SDA....................................-0.3V to +4V SHDNOUT ................................................................-0.3V to +6V LRCLKS1, BCLKS1, SDOUTS1, SDINS1....................................................-0.3V to DVDD + 0.3V LRCLKS2, BCLKS2, SDOUTS2, SDINS2 ................................................-0.3V to DVDDS2 + 0.3V Short Circuit to AGND Duration: HPL, HPR, REC .......................................................Continuous LSPK+, LSPK-, RSPK+, RSPK- ..........Subject to Maximum Package Power Dissipation INTMICBIAS, EXTMICBIASL, EXTMICBIASR.............Continuous Short Circuit to AVDD Duration EXTMICBIASL, EXTMICBIASR ................................Continuous Current Into/Out of Any Pin (unless otherwise noted).......100mA Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN (derate 40mW/C above +70C) .....3200mW Junction Temperature ......................................................+150C Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
MAX9851/MAX9853
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Analog Supply Voltage Digital Supply Voltage Speaker Supply Voltage SYMBOL AVDD, CPVDD DVDD, DVDDS2 PVDD CONDITIONS AVDD = CPVDD, no load No load No load Stereo headphone DAC playback mode, no output loads (Note 1) Stereo speaker (MAX9851)/line output (MAX9853) Mono receiver Stereo headphone Analog Supply Current AIDD Line only playback mode, no output loads Stereo speaker (MAX9851)/line output (MAX9853) Mono receiver Stereo headphone DAC plus line input playback mode, no output loads (Note 1) Stereo speaker (MAX9851)/line output (MAX9853) Mono receiver MIN 2.6 1.7 2.6 7.2 6.5 6.4 5.0 4.6 4.4 7.2 6.4 6.3 mA 8.5 TYP MAX 3.3 3.3 5.5 UNITS V V V
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER SYMBOL CONDITIONS Stereo headphone Full-duplex voice mode, no output loads Stereo speaker (MAX9851)/line output (MAX9853) Mono receiver Analog Supply Current AIDD Full-duplex voice mode plus DAC playback mode, no output loads (Notes 1, 2) Stereo headphone Stereo speaker (MAX9851)/line output (MAX9853) Mono receiver MIN TYP 11.9 11.2 11.1 11.9 mA 11.2 11.1 12.2 18.2 5 10 2 2.7 6.2 3.9 1.4 0.5 1 0.1 70 14 15 3.7 7.8 5.2 20 10 20 5 A A A ms mA 24.0 mA A 14.5 MAX UNITS
ADC record mode (Note 3) ADC record mode plus DAC headphone playback mode (Notes 1, 3) Mono Class D speaker mode Speaker Supply Current (Note 4) PIDD Stereo Class D speaker mode Sleep mode (MAX9851, MAX9853) Playback operation (Note 1), no output loads Digital Supply Current DIDD Full duplex voice operation (Note 2), no output loads, TA = +25C Record operation (Notes 1, 3) Analog Shutdown Current Digital Shutdown Current PVDD Shutdown Current (Note 4) Shutdown to Full Operation AISHDN DISHDN PISHDN tON IAVDD + ICPVDD, TA = +25C IDVDD + IDVDDS2 , TA = +25C IPVDD, TA = +25C MAX9851 MAX9853
ADC and DAC fully operational, master mode
DAC PERFORMANCE (Note 5) (DAC in Master Mode) Gain Error Channel Gain Matching fS = 8kHz (voice modes), headphone volume = +5.5dB Dynamic Range (Note 6) DR fS = 8kHz and 48kHz (stereo audio modes), headphone volume = +5.5dB 84 87.5 1 1 75.5 dB 7 % %
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER SYMBOL CONDITIONS fIN = 1kHz, fS = 8kHz, 0dBFS (voice mode master mode, ADC and headphone output enabled, no load), headphone volume = +2.5dB fIN = 1kHz, fS = 48kHz, 0dBFS (ADC and headphone output enabled, no load), headphone volume = +2.5dB fIN = 1kHz, fS = 8kHz and 16kHz (voice modes), headphone volume = +2.5dB Signal-to-Noise Ratio (Note 7) SNR fIN = 1kHz, fS = 8kHz to 48kHz (stereo audio modes), headphone volume = +2.5dB Crosstalk Power-Supply Rejection Ratio DAC DIGITAL FILTERS Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Attenuation at fS / 2 DAC VOICEBAND HIGHPASS FILTER (S1 Mono Voice Input Path, fS = 8kHz, Register 0x07 bit 4 = 1) Passband Cutoff Passband -3dB Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff Passband -3dB Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation fSL f > fSL 75 fPL f < fPL fSH f < fSH fPH fP3_H f > fPH 154 28 3500 0.05 3900 fSH f < fSH fPH fP3_H f > fPH 77 28 350 260 0.2 175 130 0.2 Hz Hz dB Hz dB Hz Hz dB Hz dB Hz dB Hz dB fSD f > fSD 60 -6.02 fPD f < fPD 0.44 0.2 0.58 fS dB fS dB dB XTALK PSRR Driven channel at -1dBFS, fIN = 1kHz, fS = 8kHz, headphone output (no load) f = 217Hz, VRIPPLE = 100mVP-P f = 10kHz, VRIPPLE = 100mVP-P 88 -95 95 68 dB dB MIN TYP MAX UNITS
MAX9851/MAX9853
-71.5 dB -84.5
Total Harmonic Distortion Plus Noise
THD+N
75.5 dB
DAC VOICEBAND HIGHPASS FILTER (S1 Mono Voice Input Path, fS = 16kHz, Register 0x07, bit 4 = 1)
DAC VOICEBAND LOWPASS FILTER (S1 Mono Voice Input Path, fS = 8kHz)
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Stopband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation DAC ADJUSTABLE HIGHPASS FILTER DC Attenuation Highpass Cutoff (-3dB) DCATT fP Register 0x07 bits [3:0] = 0x5, 0xA, or 0xF Register 0x07 [3:0] = 0x5 Register 0x07 [3:0] = 0xA Register 0x07 [3:0] = 0xF DAC INPUT GAIN CONTROL (Register 0x0C and 0x0D) Gain Control Range ADC DC ACCURACY Gain Error Full-Scale Conversion Channel Gain Matching ADC DYNAMIC SPECIFICATIONS (Note 8) BW = 22Hz to fS / 2 (8kHz voice modes) Dynamic Range (Note 6) DR BW = 22Hz to 20kHz (48kHz stereo audio modes, A-weighted) TA = +25C TA = TMIN to TMAX 73 77 71 -85.5 -85.5 -85.5 75 81.5 87.5 dB dB 75 82 dB 0dBFS fIN = 1kHz, line input, PGA = 0dB 1 2.05 1 7 % VP-P % For both input data interfaces -96 0 dB 55 171 327 90 91 279 533 Hz dB fSL f > fSL 75 SYMBOL fPL f < fPL CONDITIONS MIN 7000 0.05 7800 TYP MAX UNITS Hz dB Hz dB
DAC VOICEBAND LOWPASS FILTER (S1 Mono Voice Audio Input Path, fS = 16kHz)
BW = 22Hz to fS / 2 (8kHz audio mode) 1kHz, 0dBFS, fS = 8kHz (voice mode) Total Harmonic Distortion THD 1kHz, 0dBFS, fS = 48kHz (stereo audio mode) 1kHz, 0dBFS, fS = 8kHz (voice mode) Signal-to-Noise Ratio SNR 1kHz, 0dBFS, fS = 48kHz (stereo audio mode, A-weighted) 1kHz, 0dBFS, fS = 8kHz (stereo audio mode, A-weighted) Channel Crosstalk Driven channel at -1dBFS, fIN = 1kHz, fS = 48kHz (from MICL to ADCR or MICR to ADCL) AVDD = 2.6V to 3.3V PSRR f = 217Hz, VRIPPLE = 100mVP-P f = 10kHz, VRIPPLE = 100mVP-P 48
-75 63 63 50
dB
Power-Supply Rejection Ratio (Note 9)
dB
6
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Attenuation at fS/2 ADC VOICEBAND HIGHPASS FILTER (S1 Mono Voice Input Path, fS = 8kHz) Passband Cutoff Passband -3dB Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff Passband -3dB Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation Passband Cutoff Passband Ripple Stopband Cutoff Stopband Attenuation ADC DC-BLOCKING FILTER DC-Blocking Filter -3dB Corner DC Attenuation Maximum DC Input DAC/ADC DATA RATE ACCURACY LRCLK Output Sample Rate Deviation From Ideal (Note 10) fS = 8kHz to 48kHz (master mode with DAC only enabled) (See Table 1 for details) -0.025 +0.025 % fC As a fraction of output sample rate fS / 1608 120 0.125 Hz dB V fSL f > fSL 75 fPL f < fPL fSL f > fSL 75 7000 0.05 7800 fPL f < fPL fSH f < fSH fPH fP3_H f > fPH 154 28 3500 0.05 3900 fSH f < fSH fPH fP3_H f > fPH 77 28 350 260 0.2 175 130 0.2 Hz Hz dB Hz dB Hz Hz dB Hz dB Hz dB Hz dB Hz dB Hz dB fSBL f > fSBL 53 -6.02 SYMBOL fPBL f < fPBL CONDITIONS MIN 0.44 0.5 0.58 TYP MAX UNITS fS dB fS dB dB
MAX9851/MAX9853
ADC DIGITAL FILTER PATH (Stereo Audio Modes)
ADC VOICEBAND HIGHPASS FILTER (S1 Mono Voice Input Path, fS = 16kHz)
ADC VOICEBAND LOWPASS FILTER (S1 Mono Voice Input Path, fS = 8kHz)
ADC VOICEBAND LOWPASS FILTER (S1 Mono Voice Input Path, fS = 16kHz)
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER SYMBOL CONDITIONS fS = 8kHz (voice mode) fS = 16kHz (voice mode) fS = 8kHz LRCLK Output Sample Rate Deviation From Ideal (Note 10) Master mode with ADC SDOUT enabled; audio mode, unless otherwise noted fS = 11.025kHz fS = 12kHz fS = 16kHz fS = 22.05kHz fS = 24kHz fS = 32kHz fS = 44.1kHz fS = 48kHz LRCLK Input Sample Rate Range DAC TRANSDUCER/VIBE OUTPUT Vibe PGA Range 0dBFS Output Voltage Output Offset Voltage Vibe PGA Output Resolution LPF Passband -3dB Cutoff LPF Stopband Attenuation 1-Bit DAC Digital Dynamic Range 1-Bit DAC Operating Frequency Output High Current Output Low Voltage PGAR fS = 8kHz, 16kHz, or 32kHz fPBL fSBL DRV fV IOH VOL VOUT = DVDD IOL = 3mA fS = 11.025kHz, 22.05kHz, or 44.1kHz fS = 12kHz, 24kHz, or 48kHz f > 3.5xfPBL Ideal dynamic range (0 to 8kHz or 0 to fS / 2 for fS < 16kHz) 27 48 650 3 0.4 TGAIN 11 steps in 6dB increments 1-bit DAC output externally filtered pullup resistor to DVDD (TGAIN = 0dB) 1-bit DAC output externally filtered, no signal, pullup resistor to DVDD -30 DVDD / 2 DVDD / 2 10 483 665 724 dB dB kHz A V Hz +30 dB VP-P V bits Synchronous or asynchronous input (slave mode with only DAC enabled) 7.8 MIN TYP MAX UNITS
DAC/ADC DATA RATE ACCURACY 0 0 0.31 0.27 0.31 -0.43 -0.41 0.31 -0.43 -1.74 -0.43 50 kHz %
OPEN-DRAIN DIGITAL OUTPUT (VIBE)
8
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER HEADPHONE AMPLIFIERS Output Power 0dBFS Output Voltage Line In to HP Out Voltage Gain Output Offset Voltage Total Harmonic Distortion Plus Noise VOS RL = 32, POUT = 50mW, f = 1kHz, BW = 22Hz to 20kHz THD+N RL = 16, POUT = 60mW, f = 1kHz, BW = 22Hz to 20kHz DR +5.5dB volume setting (DAC input to HP output), A-weighted AVCC = 2.6V to 3.6V PSRR CL VRIPPLE = 100mVP-P, f = 217Hz VRIPPLE = 100mVP-P, f = 10kHz Maximum Capacitive Load Crosstalk (Line Input to Headphone Output) Channel Gain Matching AVMATCH No sustained oscillations RL = 32, POUT = 1.6mW, f = 1kHz Line input to headphone output Peak voltage, 32samples per second, A-weighted, RL = 32 (Note 11) Into shutdown, HP disabled Out of shutdown, HP enabled 70 60 0.03 87.5 95 95 68 150 -85 1 -53 dBV -48 pF dB % dB dB POUT f = 1kHz, THD < 1%, volume +5.5dB RL = 16 RL = 32 30 3.14 1.54 3.1 80 55 3.38 1.66 3.35 10 0.03 % 3.62 1.78 3.6 40 mW VP-P V/V mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9851/MAX9853
+4.5dB volume setting, input is full-scale signal from the audio DAC +4.5dB volume setting Stereo/mono Balanced mono
Dynamic Range Power-Supply Rejection Ratio (DAC Input to HP Out)
Click-and-Pop Level
KCP
SPEAKER AMPLIFIERS (MAX9851) (Note 12) PVDD = 3.3V, THD+N < 1% f = 1kHz, 2VP-P line input, +13.1dB speaker amp volume setting PVDD = 5V, THD+N < 1% PVDD = 3.3V, THD+N < 10% PVDD = 5V, THD+N < 10% 0dBFS Output Voltage RL = 8 RL = 8 RL = 8 RL = 8 500 1150 mW 600 1250 8.4 VP-P
Output Power
POUT
+12.1dB volume setting, PVDD = +5V
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Line In to Speaker Out Voltage Gain Output Offset Voltage Total Harmonic Distortion Plus Noise Dynamic Range Power-Supply Rejection Ratio Crosstalk Channel Gain Matching Class D Switching Frequency Peak voltage, 32Into shutdown samples per second, A-weighted Out of shutdown RL = 8 (Note 11) POUT = 1W per channel, RL = 8 AVMATCH VOS THD+N DR PSRR RL = 8, POUT = 125mW, f = 1kHz, BW = 22Hz to 20kHz, +10.1dB volume setting +12.1dB volume setting, A-weighted PVDD = 2.6V to 5.5V VRIPPLE = 100mVP-P, f = 217Hz VRIPPLE = 100mVP-P, f = 10kHz RL = 8, POUT = 100mW, f = 1kHz 50 SYMBOL CONDITIONS +12.1dB volume setting, PVDD = +5V MIN 4.0 TYP 4.2 10 0.03 90 70 70 55 60 4 1100 -35 dBV -35 75 % dB % kHz dB MAX 4.4 100 UNITS V/V mV % dB
Click-and-Pop Level Efficiency Line Output Common-Mode Voltage Line Output Differential Offset Voltage Maximum Differential Output Voltage Dynamic Range Total Harmonic Distortion Plus Noise Power-Supply Rejection Ratio Line Input to Line Output Gain Accuracy
KCP
LINE OUTPUT AMPLIFIERS (MAX9853) (Note 12) 1.13 -90 3.16 DR THD+N 1.4mVRMS (-60dB) output voltage, A-weighted fIN = 1kHz, VOUT = 2VP-P, BW = 22Hz to 20kHz AVDD = 2.6V to 3.6V PSRR VRIPPLE = 100mVP-P, f = 217Hz VRIPPLE = 100mVP-P, f = 20kHz -0.4 57 4.16 88 0.004 100 95 55 +0.6 dB dB 1.23 1.33 +90 4.74 V mV VP-P dB %
10
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER RECEIVER AMPLIFIER (Note 12) RL = 16, input signal from LINEIN1 Output Power POUT f = 1kHz, THD < 1%, +5.5dB volume setting RL = 16, input signal is the sum of LINEIN1+LINEIN2 RL = 32, input signal from LINEIN1 Maximum Output Voltage +4.5dB volume setting, 0dB PGA setting, input signal 0dBFS from DAC output, only 1 input selected +4.5dB volume setting, 0dB PGA setting, only 1 input selected VOS RL = 32, POUT = 40mW, f = 1kHz, BW = 22Hz to 20kHz, +3dB volume setting THD+N RL = 16, POUT = 40mW, f = 1kHz, BW = 22Hz to 20kHz, +3dB volume setting DR PSRR CL KCP +6dB volume setting, A-weighted AVDD = 2.6V to 3.3V Power-Supply Rejection Ratio Maximum Capacitive Load Click-and-Pop Level VOLUME CONTROL/PGAs Headphone/Receiver Volume Control Range Headphone/Receiver Mute Attenuation Speaker Volume Control Range (MAX9851) Speaker Mute Attenuation (MAX9851) Differential Line Output Gain Control Range (MAX9853) Differential Line Output Mute Attenuation (MAX9853) f = 1kHz f = 1kHz -78.4 100 f = 1kHz -72.4 100 +7.9 -80 100 +13.7 +6.1 dB dB dB dB dB dB VRIPPLE = 100mVP-P, f = 217Hz VRIPPLE = 100mVP-P, f = 20kHz No sustained oscillations Peak voltage, 32 samples per second, A-weighted, RL = 16 (Note 11) 60 0.04 92 100 98 65 150 -44.6 pF dBV dB dB 35 80 SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9851/MAX9853
105
mW
55
3.09
3.35
3.64
VP-P
Line In to REC Out Voltage Gain Output Offset Voltage Total Harmonic Distortion Plus Noise Dynamic Range
1.54
1.68 10 0.03
1.82 60
V/V mV
%
______________________________________________________________________________________
11
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Sidetone Volume Control Range Sidetone Mute Attenuation CHARGE PUMP Charge-Pump Oscillator Frequency MICROPHONE AMPLIFIERS Preamplifier Gain MIC PGA Gain MIC Mute Attenuation Common-Mode Rejection Ratio MIC Input Voltage Range MIC Input Resistance MIC GND Sense Input Resistance MIC Input Resistance Matching MIC Input Bias Voltage Input Voltage Noise RIN_MIC RIN_MICS RMATCH VCML EIN_MIC CMRR AVPRE AVMICPGA EXTMIC_ AVPRE = +20dB AVPRE = +20dB +18.5 -0.9 -0.9 +18.5 105 80 -1 -0.1 30 15 50 25 0.3 -0.1 0 25 0.035 +0.1 +1 +0.1 70 36 +20.5 +0.4 +0.4 +20.5 dB dB dB dB V k k % V nV/Hz fOSC 295 650 1200 kHz f = 1kHz, sidetone deselected from input mixer SYMBOL CONDITIONS MIN -34.0 80 TYP MAX +30.5 UNITS dB dB
PGA gain = 0dB PGA gain = +20dB f = 1kHz EXTMIC_, VIN = 100mVP-P at 217Hz, AVPRE = +20dB INTMIC_, EXTMIC_ EXTMICGND INTMIC_, EXTMIC_ EXTMICGND INTMICP to INTMICN or EXTMICL to EXTMICR Measured at INTMIC_, EXTMIC_, and EXTMICGND f = 1kHz, AVPRE = +20dB, RSOURCE = 0 AVPRE = 0dB, AVMICPGA = 0dB, VIN = 2VP-P, f = 1kHz, BW = 22Hz to 20kHz
Total Harmonic Distortion Plus Noise
THD+N
AVPRE = +20dB, AVMICPGA = 0dB, VIN = 200mVP-P, f = 1kHz, BW = 22Hz to 20kHz AVPRE = +20dB, AVMICPGA = +20dB, VIN = 20mVP-P, f = 1kHz, BW = 22Hz to 20kHz AVDD = 2.6V to 3.3V, TA = +25C 48
0.035
%
0.06 65 65 65 dB dB dB
MIC Power-Supply Rejection Ratio
PSRR
VRIPPLE = 100mVP-P at 217Hz, output referred VRIPPLE = 100mVP-P at 10kHz, output referred
12
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER MICROPHONE BIAS INTMICBIAS Output Voltage INTMICBIAS Load Regulation INTMICBIAS Minimum Capacitive Load INTMICBIAS Short-Circuit Current INTMICBIAS Power-Supply Rejection Ratio INTMICBIAS Noise Voltage EXTMICBIAS_ Output Impedance EXTMICBIAS_ Off-Impedance LINE INPUT (Note 13) Line Input Maximum Input Voltage Line Input Resistance Line Channel-to-Channel Gain Matching PGA Gain Range HEADSET AUTO-DETECT (Normal Operation) MIC Sense High Threshold MIC Sense Low Threshold MIC Sense Deglitch Period Headphone Sense Current Headphone Sense Voltage Headphone Sense Threshold SLEEP MODE (AVCC = 0V or 3V) MIC Sense Current MIC Sense Voltage MIC Sense Sleep Threshold IMIC VMIC VTH4 Voltage at EXTMICBIASL 0.9 EXTMICBIASL = AGND 3 PVDD 2 2.7 10 A V V VTH1 VTH2 tGLITCH ISENSE VSENSE VTH3 MIC bias and bias resistor enabled MIC bias and bias resistor enabled Pulses shorter than tGLITCH1 are eliminated VHPL / VHPR = AGND (headphones disabled) HPR/HPL (headphone amplifiers disabled) Test 2 (HPTEST = 1) - HPR only 0.74 x AVDD 0.92 x 0.95 x 0.98 x VMICBIAS VMICBIAS VMICBIAS 0.06 x 0.1 x 0.17x VMICBIAS VMICBIAS VMICBIAS 20 3.4 AVDD 0 0.73 x AVDD 0.82 x AVDD 5 V V ms A V V RIN AVMATCH -34.0 10 2 20 1 +30.5 VP-P k % dB PSRR To AGND AVDD = 2.6V to 3.3V, TA = +25C VRIPPLE = 100mV at 217Hz VRIPPLE = 100mV at 10kHz VNOISE REXTMIC f = 22Hz to 20kHz f = 1kHz 2.2k setting 470 setting VEXTMICBIAS_ = 0 to 3.0V 2.00 425 1 2 VMICBIAS IMICBIAS = 0 to 2mA 2.3 2.4 0.7 1 15 72 85 70 2.8 20 2.42 515 2.5 10 V F mA dB dB dB VRMS nV/Hz k M SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9851/MAX9853
______________________________________________________________________________________
13
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
TIMING CHARACTERISTICS
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER MCLK Input Frequency MCLK Duty Cycle Maximum MCLK Jitter Maximum allowable RMS for performance limits SYMBOL fMCLK 45 CONDITIONS MIN TYP 13 / 26 50 100 55 MAX UNITS MHz % psRMS
INPUT CLOCK CHARACTERISTICS
DIGITAL INPUTS (BCLKS_, LRCLKS_, SDINS_, MCLK, SDA, SCL, FAULTIN) Input-Voltage High Input-Voltage Low Input Hysteresis Input Leakage Current FAULTIN Input Low Leakage Current (MAX9853) FAULTIN Input High Leakage Current (MAX9853) Input Capacitance CMOS DIGITAL OUTPUTS (BCLKS_, LRCLKS_, SDOUTS_) Output Low Voltage Output High Voltage VOL VOH IOL = 3mA IOH = 3mA DVDD 0.4 75 308 30 30 7 30 5 35 50 0.4 V V IIH, IIL IIL IIH 10 FAULTIN has internal pullup resistor -3 VIH VIL 200 +3 30 3 0.7 x DVDD 0.3 x DVDD V V mV A A A pF
DIGITAL AUDIO INTERFACE TIMING CHARACTERISTICS (Digital Audio Interface S1 and S2) BCLK Cycle Time BCLK High Time BCLK Low Time BCLK_ or LRCLK_ Rise and Fall Time SDIN_ or LRCLK_ to BCLK_ Rising Set-Up Time SDIN_ or LRCLK_ to BCLK_ Rising Hold Time SDOUTS1 Delay Time SDOUTS2 Delay Time tBCLKS tBCLKM tBCLKH tBCLKL tr, tf tSU tHD tDLY tDLY Slave operation Master operation Slave operation Slave operation Master operation, CL = 15pF BCI = 0 (see I C register definition) BCI = 0 (see I C register definition) BCI = 0 (see I C register definition), CL = 30pF BCI = 0 (see I C register definition), CL = 30pF
2 2 2 2
ns ns ns ns ns ns ns ns ns
14
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
TIMING CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER BCLK_ Cycle Time BCLK_ High Time BCLK_ Low Time BCLK_ or LRCLK_ Rise and Fall Time SDIN_ or LRCLK_ to BCLK_ Rising Edge Setup Time SDIN_ or LRCLK_ to BCLK_ Rising Edge Hold Time SDOUTS1 Delay Time SDOUTS2 Delay Time SYMBOL tBC tBH tBL tr, tf tSU tHD tDLY tDLY Master mode, CLOAD = 15pF BCI = 0 (see I2C register definition) BCI = 0 (see I2C register definition) BCI = 0 (see I2C register definition), from BCLK rising edge BCI = 0 (see I2C register definition), from BCLK rising edge VOUT = DVDD IOL = 3mA for DVDD > 2V Output Low Voltage VOL IOL = 3mA for DVDD < 2V 30 5 35 50 CONDITIONS MIN 75 30 30 7 TYP MAX UNITS ns ns ns ns ns ns ns ns
MAX9851/MAX9853
VOICE MODE TIMING CHARACTERISTICS (Digital Audio Interface S1 and S2)
OPEN-DRAIN DIGITAL OUTPUTS (SDA, IRQ) Output High Current IOH 3 0.4 0.2 x DVDD 3 0.4 0 1.3 0.6 1.3 0.6 0.6 400 V A
OPEN-DRAIN DIGITAL OUTPUT (SHDNOUT) (MAX9853 Only) Output High Current Output Low Voltage I2C TIMING CHARACTERISTICS Serial Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition SCL Pulse Width Low SCL Pulse Width High Setup Time for a Repeated START Condition fSCL tBUF tHD,STA tLOW tHIGH tSU,STA kHz s s s s s IOH VOL VOUT = DVDD IOL = 100A A V
______________________________________________________________________________________
15
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
TIMING CHARACTERISTICS (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = 10k, ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CNREG = CPREG = CINTMICBIAS, CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (See Functional Diagrams/Typical Operating Circuits).
PARAMETER Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time SDA and SCL Receiving Fall Time SYMBOL tHD,DAT tSU,DAT tr tf (Note 14) (Note 14) DVDD = 1.8V (Note 14) SDA Transmitting Fall Time tf DVDD = 3.3V (Note 14) Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike tSU,STO Cb tSP 0 20+0.05Cb 0.6 400 50 250 s pF ns CONDITIONS MIN 0 100 20+0.1Cb 20+0.1Cb 20+0.1Cb 300 300 250 ns TYP MAX 900 UNITS ns ns ns ns
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11:
Note 12: Note 13: Note 14:
DAC playback mode is defined as clocking all zeros into the DAC which operates in stereo audio mode at the 48kHz sample rate in master mode. Full-duplex voice mode is defined as operating the DAC and ADC in mono 8kHz voice mode with line inputs, microphone inputs, and an analog output enabled. Record operation is defined as operating the stereo ADC with the stereo external microphone inputs enabled at the 48kHz sample rate in master mode. Speaker output available only on the MAX9851. PVDD powers only the headset autodetect circuitry when in sleep mode on the MAX9853. DAC performance measured at headphone outputs. Dynamic range measured using the EIAJ method. The input is applied at -60dBFS, fIN = 1kHz. The THD+N referred to 0dBFS A-weighted. The SNR is referred to 0dBFS A-weighted. ADC performance measured from line inputs (unless otherwise noted). Microphone amplifiers connected to ADC, mic inputs AC-grounded. In master-mode operation, sample clock rate is proportional to MCLK input. Speaker amplifier testing performed with 8 resistive load in series with a 68H inductive load connected across BTL outputs. Headphone and receiver amplifier testing performed with 32 resistive load connected to GND. Mode transitions are controlled by toggling the amplifier on and off using the corresponding enable bit. Units expressed in dBV. Input signal for speaker, line output, and receiver output performance measured using line inputs. Line input specifications measured from line inputs to line outputs. CB is in pF.
16
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
TYPICAL POWER DISSIPATION (No Output Load)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +2.7V.)
MODE DAC playback mode operating at 48kHz sampling rate OUTPUT AMPLIFIER Stereo headphone Stereo speaker Mono receiver Stereo headphone Line-only playback mode Stereo speaker Mono receiver Stereo headphone DAC and line input playback mode operating at 48kHz sampling rate Stereo speaker Mono receiver Stereo headphone 8kHz voice mode with mono DAC, mono ADC, line inputs and a mono microphone enabled 8kHz voice mode and 48kHz stereo audio mode with stereo DAC, mono ADC, line inputs and a mono microphone enabled ADC record mode with stereo microphone and line inputs enabled ADC record and stereo playback with stereo microphone and stereo headphones Stereo speaker Mono receiver Stereo headphone Stereo speaker Mono receiver -- -- TOTAL POWER (mW) 27 55 24 16 44 14 27 55 25 48 76 46 53 81 51 46 57
MAX9851/MAX9853
Typical Operating Characteristics
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HP)
MAX9851/53 toc01
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO HP)
MAX9851/53 toc02
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO RECEIVER)
RECEIVER GAIN = +5.5dB RL = 32 AVDD = 3.0V 10kHz 1kHz
MAX9851/53 toc03
100 HP GAIN = +5.5dB RL = 32 AVDD = 3.0V
100 HP GAIN = +5.5dB RL = 16 AVDD = 3.0V
100
10
10
10
THD+N (%)
THD+N (%)
1 10kHz
1 10kHz 0.1
THD+N (%)
1kHz
1
0.1
0.1
0.01 20Hz 0.001 0 10 20 30 40 50 60 70 OUTPUT POWER (mW) 1kHz
0.01 20Hz 0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW)
0.01
20Hz
0.001 0 20 40 60 80 100 120 OUTPUT POWER (mW)
______________________________________________________________________________________
17
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO RECEIVER)
MAX9851/53 toc04
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER AMP)
MAX9851/53 toc05
TOTAL HARMONIC DISTORTION PLUS NOISE vs. OUTPUT POWER (DAC TO SPEAKER AMP)
SPEAKER AMP GAIN = +13.1dB RL = 8 + 68H PVDD = 5.0V MAX9851 20Hz
MAX9851/53 toc06
100 RECEIVER GAIN = +5.5dB RL = 16 AVDD = 3.0V 10kHz THD+N (%) 1
100 SPEAKER AMP GAIN = +13.1dB RL = 8 + 68H PVDD = 3.3V MAX9851 10kHz
100
10
10
10
THD+N (%)
THD+N (%)
1
1 10kHz 0.1
20Hz
0.1
1kHz 20Hz
0.1 1kHz
0.01
0.01
0.01
1kHz
0.001 0 20 40 60 80 100 120 140 160 OUTPUT POWER (mW)
0.001 0 200 400 600 800 OUTPUT POWER (mW)
0.001 0 500 1000 1500 OUTPUT POWER (mW)
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HP)
MAX9851/53 toc07
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO HP)
MAX9851/53 toc08
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO RECEIVER)
RECEIVER GAIN = +5.5dB RL = 16 AVDD = 3.0V 1
MAX9851/53 toc09
10 HP GAIN = +5.5dB RL = 16 AVDD = 3.0V 1 THD+N (%)
10 HP GAIN = +5.5dB RL = 32 AVDD = 3.0V
10
1 THD+N (%)
0.1 20mW 0.01 52mW
20mW 0.1
THD+N (%) 0.1 20mW 40mW 0.01 1k 10k 100k
72mW
60mW 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 100 FREQUENCY (Hz) 10 100 1k FREQUENCY (Hz) 10k 100k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO RECEIVER)
RECEIVER GAIN = +5.5dB RL = 32 AVDD = 3.0V 1 THD+N (%) THD+N (%)
MAX9851/53 toc10
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER AMP)
SPEAKER AMP GAIN = +13.1dB PVDD = 5.0V MAX9851 1 THD+N (%)
MAX9851/53 toc11
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (DAC TO SPEAKER AMP)
SPEAKER AMP GAIN = +13.1dB PVDD = 3.3V MAX9851 1
MAX9851/53 toc12
10
10
10
0.1
32mW
0.1
0.1 8 200mW 1k FREQUENCY (Hz) 10k 100k
60mW 0.01 10 100 1k FREQUENCY (Hz) 10k 100k 0.01 10
8, 1W 100
8, 0.2W 0.01 1k FREQUENCY (Hz) 10k 100k 10
8 430mW 100
18
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (INTERNAL MIC TO ADC) vs. FREQUENCY (LINE IN TO ADC) vs. FREQUENCY (DAC TO LINE OUT)
MAX9851/53 toc13 MAX9851/53 toc14
VOUT = 2VP-P RL = 10k fS = 48kHz MAX9853 1 THD+N (%)
ADC INPUT VOLTAGE = 2VP-P (0dBFS) 1 THD+N (%)
ADC INPUT VOLTAGE = 2VP-P (0dBFS) 8kHz VOICE MODE 1 THD+N (%) MIC GAIN = 0dB 0.1 MIC GAIN = 40dB MIC GAIN = 20dB
0.1 8kHz VOICE MODE 0.01
0.1
RIGHT 0.01 48kHz MASTER MODE DC-BLOCKING FILTER OFF 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 10 100 1k FREQUENCY (Hz) 10k 100k 0.001 10 LEFT
0.01
100
1k FREQUENCY (Hz)
10k
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (INTERNAL MIC TO ADC)
MAX9851/53 toc16
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY (LINE IN TO LINE OUT)
MAX9851/53 toc17
SPEAKER AMP EFFICIENCY vs. OUTPUT POWER
80 70 EFFICIENCY (%) 60 50 40 30 20 10 RL = 8 68H
MAX9851/53 toc18
10 ADC INPUT VOLTAGE = 2VP-P (0dBFS) 48kHz NONVOICE MODE 1 THD+N (%)
10 NO LOAD MAX9853 1 THD+N (%)
90
0.1
MIC GAIN = 40dB MIC GAIN = 20dB
0.1 LEFT 0.01
0.01
MIC GAIN = 0dB
0.001 10 100 1k FREQUENCY (Hz) 10k 100k
0.001 10 100 1k
RIGHT 10k 100k
PVDD = 5V fIN = 1kHz 0 1 2 OUTPUT POWER (W) 3 4
0
FREQUENCY (Hz)
SPEAKER AMP EFFICIENCY vs. OUTPUT POWER
MAX9851/53 toc19
SPEAKER AMP OUTPUT POWER vs. LOAD RESISTANCE
3.5 OUTPUT POWER (W) 3.0 2.5 2.0 1.5 1.0 5.0V 3.3V fIN = 1kHz 33H IN SERIES WITH RLOAD THD+N = 1%
MAX9851/53 toc20
SPEAKER AMP OUTPUT POWER vs. SUPPLY VOLTAGE (PVDD)
1.6 1.4 OUTPUT POWER (W) 1.2 1.0 THD+N = 10% 0.8 0.6 0.4 0.2 0 fIN = 1kHz RL = 8 + 68H 2.5 3.5 4.5 5.5 THD+N = 1%
MAX9851/53 toc21
90 80 70 EFFICIENCY (%) 60 50 40 30 20 10 0 0 1 2 OUTPUT POWER (W) 3 4 PVDD = 3.0V fIN = 1kHz RL = 8 68H
4.0
1.8
0.5 0 1 10 100 1000 LOAD RESISTANCE ()
SUPPLY VOLTAGE (V)
______________________________________________________________________________________
19
MAX9851/53 toc15
10
10
10
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
HEADPHONE AMP OUTPUT POWER vs. SUPPLY VOLTAGE (AVDD)
MAX9851/53 toc22
HEADPHONE AMP OUTPUT POWER vs. SUPPLY VOLTAGE (AVDD)
MAX9851/53 toc23
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO HP)
-10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 -110 -120 3.6 10 100 1k FREQUENCY (Hz) 10k 100k VRIPPLE = 100mVP-P AC SIGNAL APPLIED TO AVDD AND CPVDD
MAX9851/53 toc24
90 80 70 OUTPUT POWER (mW) 60 50 40 30 20 10 0 2.6 2.8 3.0 3.2 3.4 fIN = 1kHz RL = 32 HP GAIN = 95.5dB THD+N = 1% THD+N = 10%
140 120 OUTPUT POWER (mW) 100 80 60 40 20 0 fIN = 1kHz RL = 16 HP GAIN = 95.5dB 2.6 2.8 3.0 3.2 3.4 THD+N = 1% THD+N = 10%
0
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO RECEIVER)
MAX9851/53 toc25
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO LINE OUT)
MAX9851/53 toc26
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY (DAC TO SPEAKER)
-10 -20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -100 -110 -120 VRIPPLE = 100mVP-P AC SIGNAL APPLIED TO PVDD ONLY MAX9851
MAX9851/53 toc27
0 -10 -20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -100 -110 -120 10 100 1k FREQUENCY (Hz) 10k VRIPPLE = 100mVP-P AC SIGNAL APPLIED TO AVDD AND CPVDD
0 -10 -20 -30 -40 PSRR (dB) -50 -60 -70 -80 -90 -100 -110 -120 VRIPPLE = 100mVP-P AC SIGNAL APPLIED TO AVDD AND CPVDD MAX9853
0
100k
10
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k FREQUENCY (Hz)
10k
100k
FFT, DAC TO LINE OUT 8kHz SLAVE VOICE MODE, 0dBFS
MAX9851/53 toc28
FFT, DAC TO LINE OUT 8kHz MASTER VOICE MODE, 0dBFS
MAX9851/53 toc29
FFT, DAC TO LINE OUT 8kHz MASTER VOICE MODE, -60dBFS
MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
MAX9851/53 toc30
20 MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4
20 MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4
20
0
1
2 FREQUENCY (kHz)
3
4
20
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) FFT, DAC TO LINE OUT FFT, DAC TO LINE OUT FFT, DAC TO LINE OUT 48kHz MASTER MODE, 0dBFS 48kHz SLAVE MODE, 0dBFS 48kHz SLAVE MODE, -60dBFS
MAX9851/53 toc31 MAX9851/53 toc32
MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15
MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
MAX9853 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15
20
0
5
10 FREQUENCY (kHz)
15
20
20
FFT, LINE IN TO ADC 48kHz MASTER MODE, 0dBFS
MAX9851/53 toc34
FFT, LINE IN TO ADC 48kHz MASTER MODE, -60dBFS
MAX9851/53 toc35
FFT, LINE IN TO ADC 8kHz MASTER VOICE MODE, 0dBFS
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
MAX9851/53 toc36
20 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 5 10 FREQUENCY (kHz) 15
20 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
20
20
0
5
10 FREQUENCY (kHz)
15
20
0
1
2 FREQUENCY (kHz)
3
4
FFT, LINE IN TO ADC 8kHz MASTER VOICE MODE, -60dBFS
MAX9851/53 toc37
FFT, LINE IN TO ADC 8kHz SLAVE VOICE MODE, -60dBFS
MAX9851/53 toc38
WIDEBAND FFT (DAC TO HP AMP)
DAC INPUT = 0dBFS HP AMP GAIN = 0dB
MAX9851/53 toc39
20 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4
20 0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 0 1 2 FREQUENCY (kHz) 3 4
0 -20 VOUT AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140 10 100 1k FREQUENCY (Hz) 10k
100k
______________________________________________________________________________________
21
MAX9851/53 toc33
20
20
20
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
WIDEBAND FFT (DAC TO HP AMP)
MAX9851/53 toc40
DVDD AND DVDDS2 SUPPLY CURRENT vs. SUPPLY VOLTAGE
fS = 48kHz STEREO DAC PLAYBACK ONLY CLOCKING ZEROS INTO THE DAC SUPPLY CURRENT (mA) 15
MAX9851/53 toc41
DVDD AND DVDDS2 SUPPLY CURRENT vs. SUPPLY VOLTAGE
fS = 48kHz VOICE MODE MONO MIC MONO ADC MONO DAC CLOCKING ZEROS INTO DAC
MAX9851/53 toc42
0 -20 VOUT AMPLITUDE (dBFS) -40 -60 -80 -100 -120 -140
DAC INPUT = -60dBFS HP AMP GAIN = 0dB
20
20
SUPPLY CURRENT (mA)
15
10
10
5
5
0 10 100 1k FREQUENCY (Hz) 10k 100k 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
0 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
DVDD AND DVDDS2 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9851/53 toc43
DVDD AND DVDDS2 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9851/53 toc44
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (STEREO PLAYBACK)
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 HP AMP ENABLED RECEIVER ENABLED DACS ENABLED ADCS DISABLED MIC AMPS DISABLED CLOCKING ZEROS INTO DAC 48kHz MASTER MODE AMPS ENABLED ONE AT A TIME SPEAKER AMP ENABLED
MAX9851/53 toc45
20
20 fS = 48kHz STEREO RECORD ONLY STEREO MIC STEREO ADC MIC INPUTS AC-GROUNDED
20
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
15
15
10 fS = 8kHz VOICE + 48kHz BOTH INTERFACES ON FULL DUPLEX MONO VOICE WITH STEREO AUDIO PLAYBACK CLOCKING ZEROS INTO DACS 1.8 2.1 2.4 2.7 3.0 3.3 3.6
10
5
5
0 SUPPLY VOLTAGE (V)
0 1.8 2.1 2.4 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
0 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (ANALOG PATH)
MAX9851/53 toc46
MAX9851/53 toc47
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 0 2.6
SUPPLY CURRENT (mA)
20
SUPPLY CURRENT (mA)
DACS DISABLED ADCS DISABLED MIC AMPS DISABLED LINE IN TO AMPS AMPS ENABLED ONE AT A TIME
25
ONE DAC ENABLED ONE ADC ENABLED DIGITAL LOOPTHOUGH LEFT MIC AMP ENABLED, INPUTS GROUNDED MIC AND LINE CONNECTED TO ADC 8kHz VOICE MODE AMPS ENABLED ONE AT A TIME SPEAKER AMP ENABLED HP AMP ENABLED
25
20
S1 ENABLED (8kHz VOICE MODE) STEREO DAC ENABLED (48kHz) ONE ADC ENABLED CLOCKING ZEROS INTO DAC LEFT MIC AMP ENABLED, INPUTS GROUNDED MIC AND LINE CONNECTED TO ADC AMPS ENABLED ONE AT A TIME SPEAKER AMP ENABLED
SPEAKER AMP ENABLED HP AMP ENABLED
15
15
HP AMP ENABLED RECEIVER ENABLED
10 RECEIVER ENABLED 5 2.8 3.0 3.2 3.4 3.6 2.6
RECEIVER ENABLED
10
5 2.8 3.0 3.2 3.4 3.6 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
22
______________________________________________________________________________________
MAX9851/53 toc48
20
30
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (VOICE RECORD AND PLAYBACK)
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (DUAL DIGITAL PATH)
30
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Typical Operating Characteristics (continued)
(AVDD = CPVDD = +3V, DVDD = DVDDS2 = +1.8V, PVDD = +3.3V, RHP = 32, ZSPK = 8 + 10H, RREC = 32, ROUTL+ to ROUTL- = ROUTR+ to ROUTR- = 10k, C1 = 0.22F, C2 = CVMREG = CVPREG = CMBIAS = CREF = 1F, MCLK = 13MHz, all PGAs = 0dB, HP/REC volume = -20.0dB, SPK volume = -20.4dB, line output gain = -0.4dB, fS = 48kHz for nonvoice mode, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (STEREO RECORD)
MAX9851/53 toc49
AVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (STEREO RECORD AND PLAYBACK)
MAX9851/53 toc50
PVDD SUPPLY CURRENT vs. SUPPLY VOLTAGE (DAC TO SPEAKER AMP)
18 16 SUPPLY CURRENT (mA) 14 12 10 8 6 4 2 BOTH DACS ENABLED (48kHz) BOTH ADCS DISABLED CLOCKING ZEROS INTO DACS MIC AMPS DISABLED
MAX9851/53 toc51
30
25 SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
BOTH DACS DISABLED BOTH ADCS ENABLED (48kHz) BOTH MIC AMPS ENABLED MIC INPUTS GROUNDED
40 35 30 25 20 15 10
20
20
BOTH DACS ENABLED (48kHz) BOTH ADCS ENABLED (48kHz) CLOCKING ZEROS INTO DACS BOTH MIC AMPS ENABLED MIC INPUTS GROUNDED AMPS ENABLED ONE AT A TIME
15
HP AMP ENABLED RECEIVER
SPEAKER AMP ENABLED
10
5 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V)
0 2.6 2.8 3.0 3.2 3.4 3.6 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
DAC FREQUENCY RESPONSE 48kHz, 44.1kHz, AND 22.05kHz
MAX9851/53 toc52
ADC FREQUENCY RESPONSE 48kHz, 44.1kHz, AND 22.05kHz
MAX9851/53 toc53
DAC FREQUENCY RESPONSE 8kHz VOICE MODE
DBPE (REGISTER 0x07, B4) DBPE = 0
MAX9851/53 toc54
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100 10 100 1k FREQUENCY (Hz) 10k 22.05kHz 48kHz AND 44.1kHz
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100
DBPE = 1
100k
10
100
1k FREQUENCY (Hz)
10k
100k
10
100
1k
10k
FREQUENCY (Hz)
ADC FREQUENCY RESPONSE 8kHz VOICE MODE
ABPE (REGISTER 0x07, B5) ABPE = 0
MAX9851/53 toc55
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100 10
ABPE = 1
100
1k FREQUENCY (Hz)
10k
100k
______________________________________________________________________________________
23
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Pin Description
PIN MAX9851 1 2 3 4 5 6 7 8 9 -- -- -- MAX9853 1 2 -- -- -- -- -- -- -- 3 4 5 NAME EXTMICBIASL PREG PVDD LSPK+ LSPKPGND RSPKRSPK+ PVDD OUTL+ OUTLSHDNOUT FUNCTION Left External Microphone Bias. Provides a 2.4V microphone bias for the external microphone's left channel through selectable 2.2k or 470 output impedance resistor. Internal Positive Regulator Output. Bypass to AGND with a 1F capacitor. Left Speaker Positive Power-Supply Input. Bypass to PGND with a 0.1F capacitor. Positive Left-Channel Class D Speaker Output Negative Left-Channel Class D Speaker Output Class D Speaker Amplifier Ground Negative Right-Channel Class D Speaker Output Positive Right-Channel Class D Speaker Output Right Speaker Positive Power-Supply Input. Bypass to PGND with a 0.1F capacitor. Noninverted Differential Left-Channel Line-Level Output. OUTL+ is biased at 1.23V. Inverted Differential Left-Channel Line-Level Output. OUTL- is biased at 1.23V. Shutdown Output. Open-drain shutdown output used to control an external amplifier shutdown input through the MAX9851/MAX9853 I2C interface. Connect a 10k pullup resistor to DVDD for full output swing. Fault Input. Logic input with internal 300k pullup resistor. The state of FAULTIN is reported in status register 0x00 and can be used to trigger a hardware interrupt. Headset Autodetect Positive Power-Supply Input. Connect to PVDD battery voltage for proper headset detect operation during sleep mode (see the Headset Detect section). Connect to AVDD if not used. Bypass to AGND with a 0.1F capacitor. Inverted Differential Right-Channel Line-Level Output. OUTR- is biased at 1.23V. Noninverted Differential Right-Channel Line-Level Output. OUTR+ is biased at 1.23V. Internal Negative Regulator Output. Bypass to AGND with a 1F capacitor. Reference Output. Bypass to AGND with a 1F ceramic capacitor. Internal Microphone Bias Regulator Output. Bypass to AGND with a 1F capacitor. Line Input 1. AC-couple analog audio signal to LINEIN1. Line Input 2. AC-couple analog audio signal to LINEIN2. Audio Power-Supply Input. Bypass to AGND with 0.1F and 10F capacitors. Left-Channel Headphone Output (Stereo Mode)/Noninverting Headphone Output (Balanced Mono Mode). HPL is a DirectDrive output biased at AGND. Right-Channel Headphone Output (Stereo Mode)/Noninverting Headphone Output (Balanced Mono Mode). HPR is a DirectDrive output biased at AGND. Headphone and Receiver Amplifier Negative Supply Input. Connect to PVSS. Handset Receiver Output. REC is a DirectDrive output biased at AGND. Inverting Charge-Pump Output. Bypass to CPGND with a 1F ceramic capacitor and connect to SVSS to provide the headphone and receiver amplifiers with a negative supply.
--
6
FAULTIN
-- -- 10 11 12 13 14 15 16 17 18 19 20
7 8 9 10 11 12 13 14 15 16 17 18 19 20
PVDD OUTROUTR+ NREG REF MBIAS LINEIN1 LINEIN2 AVDD HPL HPR SVSS REC PVSS
24
______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Pin Description (continued)
PIN MAX9851 21 22 23 24 25 26 27 28 29 MAX9853 21 22 23 24 25 26 27 28 29 NAME C1N CPGND C1P CPVDD SCL SDA SDINS1 SDOUTS1 BCLKS1 FUNCTION Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.22F ceramic capacitor between C1N and C1P. Charge-Pump Ground Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.22F ceramic capacitor between C1N and C1P. Charge-Pump Positive Power-Supply Input. Bypass to CPGND with a 1F capacitor. I2C-Compatible Serial Clock Input. Connect a 10k pullup resistor to DVDD for full output swing. I2C-Compatible Serial Data Input/Output. Connect a 10k pullup resistor to DVDD for full output swing. Primary Interface Digital Audio Serial Data DAC Input. Voiceband filtering available on this input. Primary Interface Digital Audio Serial Data ADC Output. Voiceband filtering available on this output. Primary Interface Digital Audio Bit Clock Input/Output. BCLKS1 is an input when the MAX9851/MAX9853 is in slave mode and an output when in master mode. Primary Interface Digital Audio Left-Right Clock Input/Output. LRCLKS1 is the audio sample rate clock and determines whether the audio data on SDINS1 is routed to the left or right channel. LRCLKS1 is an input when the MAX9851/MAX9853 is in slave mode and an output when in master mode. Digital Ground Digital Power-Supply Input. DVDD provides power to the digital core, the I2C interface and the primary digital audio interface. Bypass to DGND with a 1F capacitor. Secondary Interface Digital Audio Left-Right Clock Input/Output. LRCLKS2 is the audio sample rate clock and determines whether the audio data on SDINS2 is routed to the left or right channel. LRCLKS2 is an input when the MAX9851/MAX9853 is in slave mode and an output when in master mode. Secondary Interface Digital Audio Bit Clock Input/Output. BCLKS2 is an input when the MAX9851/MAX9853 is in slave mode and an output when in master mode. Secondary Interface Digital Audio Serial Data ADC Output Secondary Interface Digital Audio Serial Data DAC Input
MAX9851/MAX9853
30
30
LRCLKS1
31 32
31 32
DGND DVDD
33
33
LRCLKS2
34 35 36
34 35 36
BCLKS2 SDOUTS2 SDINS2
______________________________________________________________________________________
25
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Pin Description (continued)
PIN MAX9851 37 38 39 MAX9853 37 38 39 NAME DVDDS2 MCLK VIBE FUNCTION Secondary Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1F capacitor. 13MHz/26MHz Master Clock Input Transducer/Vibrator Output. Open-drain output programmable to control a vibrator motor or a transducer. Connect a 1k pullup resistor to DVDD for full output swing. Hardware Interrupt Output. IRQ can be programmed to pull low when bits in the status register 0x00 change state. Read status register 0x00 to clear IRQ once set. Repeat faults will have no effect on IRQ until it is cleared by reading the I2C status register 0x00. Connect a 10k pullup resistor to DVDD for full output swing. External Microphone Right-Channel Single-Ended Input. Connect a compatible highimpedance or low-impedance (with built-in pre-amplifiers) microphone between EXTMICR and EXTMICGND. AC-couple a microphone to EXTMICR with a series 1F capacitor. External Microphone Left-Channel Single-Ended Input. Connect a compatible highimpedance or low-impedance (with built-in pre-amplifiers) microphone between EXTMICL and EXTMICGND. AC-couple a microphone to EXTMICL with a series 1F capacitor. Analog Ground External Microphone Ground Sense Return. AC-couple EXTMICGND to the external jack ground with a series 1F capacitor to reduce noise. Internal Positive Differential Microphone Input. AC-couple a microphone to INTMICP with a series 1F capacitor. Internal Negative Differential Microphone Input. AC-couple a microphone to INTMICN with a series 1F capacitor. Internal Microphone Bias. Bypass INTMICBIAS to AGND with a 1F capacitor. Provides 2.4V microphone bias for the internal differential microphone through an external 2.2k resistor. Right External Microphone Bias. Provides a 2.4V microphone bias for a right-channel external microphone through an internal selectable 2.2k or 470 output resistor. Exposed Thermal Pad. Connect to AGND.
40
40
IRQ
41
41
EXTMICR
42 43 44 45 46
42 43 44 45 46
EXTMICL AGND EXTMICGND INTMICP INTMICN
47
47
INTMICBIAS
48 --
48 --
EXTMICBIASR EP
26
______________________________________________________________________________________
2.6V TO 3.3V 1.7V TO 3.3V 2.6V TO 5.5V
1F 0.1F 1F 0.1F 3 9 PVDD -74dB TO +5.5dB -32dB TO +30dB HRVOLL HPL 16 PVSS -74dB TO +5.5dB HRVOLR AVDD HPR 17 PVSS AVDD REC 19 PVSS LSPK+ 4 LSPK- 5 -34dB TO +30.5dB -66.4dB TO +13.4dB SPVOLR MBIAS RSPK- 7 INTMICBIAS 47 0dB TO +20dB 0dB OR +20dB LINEIN1 PGAML LINEIN2 PALEN VOICEBAND FILTER LEFT ADC LEFT ADC INPUT MIXER 1F INTMICP 45 INTMICN 46 EXTMICBIASL 1 1F 0dB TO +20dB LINEIN1 PGAMR LINEIN2 RIGHT ADC RIGHT ADC INPUT MIXER 0dB OR +20dB PAREN EXTMICL 42 EXTMICGND 44 EXTMICBIASR 48 EXTMICR 41 1F INTERNAL REGULATORS CHARGE PUMP VIBE CONTROL CIRCUITRY VIBE 39 DVDD 1F RIGHT EXTERNAL MICROPHONE LEFT EXTERNAL MICROPHONE 1F 2.2k PGAS SIDETONE RSPK+ 8 RIGHT SPEAKER LEFT SPEAKER RECEIVER SPEAKER AVDD EXTERNAL HEADPHONE LINEIN1 PVDD 32 37 DVDDS2 DVDD 1F 0.1F 15 AVDD 24 CPVDD
1F
13 LINEIN1
PGAL1
ANALOG AUDIO SOURCE -32dB TO +30dB LINEIN2 LINEIN1 LINEIN2 LEFT DAC
MAX9851
1F
14 LINEIN2
PGAL2
SINGLE-ENDED OR BALANCED MONO OR SINGLE-ENDED MONO
33 LRCLKS2
LEFT AUDIO OUTPUT MIXER
34 BCLKS2 GAIN CONTROL PGADS2 LINEIN1 -66.4dB TO +13.4dB SPVOLL LINEIN2 RIGHT DAC DAC INPUT MIXER AND FILTER VOICEBAND FILTER MONO MIXER RIGHT AUDIO OUTPUT MIXER
SECONDARY DIGITAL AUDIO SOURCE
36 SDINS2
DIGITAL AUDIO INTERFACE S2
35 SDOUTS2
30 LRCLKS1
29 BCLKS1 GAIN CONTROL PGADS2
GSM BASEBAND PROCESSOR (VOICE DATA)
27 SDINS1
DIGITAL AUDIO INTERFACE S1
28 SDOUTS1
2.2k
1F
13MHz/ 26MHz
DVDD
INTERNAL MICROPHONE
10k
38 MCLK
40 IRQ
TIMING AND CONTROL LOGIC
DVDD
C
10k
10k
25 SCL
26 SDA
I2C SERIAL PORT
1k AGND PREG NREG 10 1F 1F 11 1F 2 43 DGND 31 CPGND 22 PGND 6 REF 12 1F C1 0.22F C2 1F MBIAS PVSS C1N C1P 23 21 20 SVSS 18 TRANSDUCER/ VIBRATOR
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
MAX9851/MAX9853
______________________________________________________________________________________
MAX9851 Functional Diagram/Typical Operating Circuit
27
MAX9851/MAX9853
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
28
2.6V TO 3.3V 1.7V TO 3.3V 2.6V TO 5.5V 1F 1F 32 37 DVDDS2 PVDD -73.5dB TO +6dB -32dB TO +30dB HRVOLL HPL 16 PVSS -73.5dB TO +6dB HRVOLR AVDD HPR 17 PVSS AVDD REC 19 PVSS OUTL+ 3 OUTL- 4 -32dB TO +30dB -71.9dB TO +7.6dB LOPGAR MBIAS OUTR- 8 INTMICBIAS 47 0dB TO +20dB 0dB TO +20dB LINEIN1 PGAML LINEIN2 PALEN VOICEBAND FILTER LEFT ADC LEFT ADC INPUT MIXER 1F INTMICP 45 INTMICN 46 EXTMICBIASL 1 1F 0dB TO +20dB LINEIN1 PGAMR LINEIN2 RIGHT ADC RIGHT ADC INPUT MIXER 0dB TO +20dB PAREN EXTMICL 42 EXTMICGND 44 EXTMICBIASR 48 EXTMICR 41 1F INTERNAL REGULATORS CHARGE PUMP VIBE CONTROL CIRCTUITRY VIBE 39 DVDD 1F RIGHT EXTERNAL MICROPHONE LEFT EXTERNAL MICROPHONE 1F 2.2k PGAS SIDETONE VOICEBAND FILTER OUTR+ 9 RIGHT OUTPUT LEFT OUTPUT EXTERNAL STEREO AMPLIFIER RECEIVER SPEAKER AVDD EXTERNAL HEADPHONE PGAL1 LINEIN1 7 DVDD 1F 0.1F 24 15 AVDD CPVDD 0.1F -32dB TO +30dB PGAL2 LINEIN2 LINEIN1 LINEIN2 LEFT DAC
1F
13 LINEIN1
ANALOG AUDIO SOURCE
MAX9853
1F
14 LINEIN2
SINGLE-ENDED OR BALANCED MONO OR SINGLE-ENDED MONO
33 LRCLKS2
LEFT AUDIO OUTPUT MIXER
34 BCLKS2 DIGITAL AUDIO INTERFACE S2 LINEIN1 -71.9dB TO +7.6dB LOPGAL LINEIN2 RIGHT DAC DAC INPUT MIXER MONO MIXER RIGHT AUDIO OUTPUT MIXER GAIN CONTROL PGADS2
SECONDARY DIGITAL AUDIO SOURCE
36 SDINS2
35 SDOUTS2
30 LRCLKS1
29 BCLKS1 DIGITAL AUDIO INTERFACE S1 GAIN CONTROL PGADS2
GSM BASEBAND PROCESSOR (VOICE DATA)
27 SDINS1
28 SDOUTS1
2.2k
1F
13MHz/ 26MHz
DVDD
INTERNAL MICROPHONE
10k
38 MCLK
40 IRQ
TIMING AND CONTROL LOGIC
DVDD
C
10k
10k
25 SCL
26 SDA
I2C SERIAL PORT
DVDD FAULTIN PREG NREG 10 1F 1F 11 1F 2 6 AGND 43 DGND 31 CPGND 22 REF 12 1F C1 0.22F C2 1F MBIAS PVSS C1N C1P 23 21 20 SVSS 18
1k TRANSDUCER/ VIBRATOR
SHDNOUT
5
______________________________________________________________________________________
10k
MAX9853 Functional Diagram/Typical Operating Circuit
TO SHUTDOWN CONTROL
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Detailed Description
The MAX9851 CODEC, with a stereo DirectDrive headphone amplifier and a stereo Class D speaker amplifier, is a complete digital audio solution for GSM/ GPRS/EDGE cell phones and PDA phones. The MAX9853 audio CODEC shares all the functionality of the MAX9851 without the Class D speaker amplifier, substituting it with stereo differential line outputs to facilitate external amplifiers and other analog audio devices. The MAX9851/MAX9853 additionally feature stereo and mono microphone inputs, and a mono DirectDrive handset receiver amplifier combined with sigma-delta stereo DACs and stereo ADCs. The sigma-delta DAC has 88dB of dynamic range and accepts stereo audio data from two independent digital audio interfaces at sampling frequencies ranging from 8kHz to 48kHz. The interfaces can accept I2S-compatible data in addition to voiceband data and allows the mixing of multiple audio sources at different unrelated sample rates. The primary digital audio input integrates bandpass filtering that can be used when operating in voice mode. Digital audio from the ADC can output on both interfaces allowing maximum flexibility. Analog and digital volume levels, muting, and device configuration are programmed through the I2C-compatible interface. Audio data is sent to and from the MAX9851/MAX9853 through either of two 4-wire digital audio data buses that support numerous formats. LRCLK and BCLK signals are generated by the MAX9851/MAX9853 when configured in master mode. The MAX9851/MAX9853 can also be configured as a slave DAC stereo audio playback device or a full duplex slave voice CODEC, accepting LRCLK and BCLK signals from an external digital audio master. Maxim's patented DirectDrive architecture employs an internal charge pump to create a negative voltage supply powering the headphone and receiver amplifier outputs. The internal negative supply allows the analog output signals to be biased at ground, eliminating the need for an output-coupling capacitor, reducing system cost and size. The MAX9851/MAX9853's stereo line inputs allow mixing of analog audio with digital audio. Numerous signal routing options and programmable gain allow any combination of analog and digital input signals at varying signal levels to be routed to any output. Sophisticated headset sensing circuitry allows the MAX9851/MAX9853 to detect a wide variety of headset configurations and trigger a hardware interrupt on jack insertion (even when powered down). The external stereo microphone inputs provide configurable internal bias resistors and a gain range of 40dB to accommodate a wide variety of microphones. The internal mono microphone input provides a differential input and a gain range of 40dB. The VIBE digital output can be used to control a vibrator, transducer, or can be used as a general-purpose digital output.
Serial Digital Audio Interface
The MAX9851/MAX9853 have two independent digital audio interfaces, S1 and S2, each capable of operating independently in the full-duplex master and slave timing modes shown in Figures 1 and 2. The second digital audio interface operates from a secondary supply voltage (DVDDS2) to allow simple integration into multiple supply systems. Set S1SDO or S2SDO to 1 (register 0x03 or 0x05, bit B7) to enable the output of ADC data to the corresponding SDOUT pin. Enabling both SDOUTS1 and SDOUTS2 will output the same digital audio signal on both interfaces and the primary S1 interface will specify the sample rate of the ADC. Set S1SDI or S2SDI to 1 (register 0x03 or 0x05, bit B6) to enable DAC input and begin an internal soft-start sequence for the corresponding SDIN pin. Clearing a particular SDI bit begins an internal soft-stop sequence prior to disabling the input. The SLD slew detect status bit (register 0x00, bit B6) indicates when a softstart/stop sequence has completed. This allows interface mode changes without interrupting the other interface's signal flow. Clear both S1SDI and S2SDI before enabling the left and right DAC with DACLEN and DACREN (register 0x1B, bits B7 and B6). To achieve the most exact sample clocks, operate the MAX9851/MAX9853 in slave mode with the exact LRCLK provided externally (in DAC-only mode) or in master mode with the ADCs disabled. The ADC requires an exact integer LRCLK frequency resulting in less accurate sample clocks than when only operating the DAC. Slave mode is only available for the DACs when the ADCs are inactive, or for fully synchronous 8kHz and 16kHz voice modes. Table 1 lists the MAX9851/MAX9853 available interface modes for each sampling frequency.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 1. Digital Audio Interface Modes
MODE 48 44.1 32 24 22.05 16 12 11.025 8 8 16 8 to 48 16 8 Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (stereo audio mode) Master (voice mode) Master (voice mode) Slave (stereo audio mode) Slave (voice mode) Slave (voice mode) fS (ADC ON) (kHz) 47.794 43.333 31.863 24.074 21.959 15.931 12.037 11.054 8.025 8.000 16.000* -- 16.000* 8.000 fS (ADC OFF) (kHz) 48.0011 44.0989 31.9986 23.9990 22.0494 15.9993 12.0010 11.0247 7.9997 8.000 16.000* 8 to 48 16.000* 8.000
*26MHz clock required for synchronous 16kHz sample rate.
Stereo Audio Modes Set S1MAS or S2MAS to 1 (register 0x04 or 0x06, bit B7) to operate the respective interface in master mode. The MAX9851/MAX9853 generate the LRCLK and BCLK signals, which can be used to send and receive digital audio samples. In stereo audio mode, the BCLK signal is a pulse with a period of 310ns. BCLK is inactive when there are no bits transmitted on SDIN or SDOUT. The number of clock cycles per frame is equal to the configured bit depth. Set S1MAS or S2MAS to 0 to operate the respective interface in slave mode, and disable the ADC in stereo audio modes (slave mode not available). The interface accepts slave mode noninteger sample clocks ranging from 8kHz to 48kHz and the appropriate bit clocks in these DAC-only stereo audio modes. See Figure 4 for the digital audio interface timing diagrams. Voice Modes In master voice mode, the S1 digital audio interface operates as shown in Figure 3. The BCLK signal is a continuous 13MHz clock. The LRCLK consists of a single-pulse frame sync signal rather than the left-/ right-frame sync clock method used in I2S. Although the 8kHz voice mode can be run from either the 13MHz or 26MHz MCLK frequency, 16kHz voice mode requires a 26MHz MCLK. Although both S1 and S2 interfaces are capable of operating in voice mode, only the primary S1 interface can be configured with a bandpass voice filter.
In slave voice mode, an external device must provide at least 16 BCLK cycles following an LRCLK pulse, which will allow operation using any BCLK rate or operation with BCLK shut off between word transfers. In voice mode, the first 16 bits of each sample treated as left-channel audio data. The MAX9851/ MAX9853 are capable of receiving up to 16 additional bits per sample word, treated as right-channel data. These additional bits are routed to the Vibe circuitry when operating in voice mode on the S1 interface. When operating on the S2 interface, these additional bits are interpreted as right-channel data, optionally routed to the right DAC and the Vibe circuitry. Additional Features Included in each digital audio interface is a timing control module allowing the MAX9851/MAX9853 to generate the clock signals for master mode. The two digital audio interfaces include full functionality for I2S modes of operation, including true I2S data, leftjustified data, and either inverted LRCLK or inverted BCLK. Set S1MODE or S2MODE to 0xA or 0xB (register 0x03 or 0x05, bits B3-B0) to configure the interface for 8kHz or 16kHz voice mode, respectively. Set S1MNO or S2MNO to 1 (register 0x03 or 0x05, bit B5) to mix the right- and left-channel input data to create a mono serial data signal from the left and right input data. The result is then input to the left digital filter path, leaving the right path unused. The output of the left filter path can still be sent to either or both the left
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
and right DACs (see the Signal Routing section). The right- and left-channel input data is summed without attenuation and may overdrive the input filter, causing distortion, when the input signals are large. The sum of the stereo input signal should not exceed the dynamic range of the filter, typically 0dBFS digital full scale. When operating in a voice mode with the primary S1 interface, the digital signal data is input to the left channel without summing since the incoming data is assumed to be mono. Adjust PGADS1 and PGADS2 (register 0x0C and 0x0D) to program the gain for the primary and secondary digital audio interfaces. Independent gain adjustment for each interface allows level-matching of different digital signal sources or fade adjustment between two signal sources.
MAX9851/MAX9853
MASTER MODE: S_WCI = 0, S_BCI = 0, S_DLY = 0, S_WS = 0 LRCLK (OUT) LEFT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 RIGHT
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Figure 1. Digital Audio Interface Timing--I2S Master Modes ______________________________________________________________________________________ 31
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
SLAVE MODE: S_WCI = 1, S_BCI = 0, S_DLY = 0, S_WS = 0 LRCLK (IN) SDIN 15 14 13 12 11 10 9 LEFT 8 7 5 4 3 2 1 0 15 14 13 12 11 10 RIGHT 9 8 7 5 4 3 2 1 0
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Figure 2. Digital Audio Interface Timing--I2S Slave Modes
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*MASTER OPERATION: LRCLK PULSE WIDTH = 1 BCLK CYCLE WIDE BCLK = CONTINUOUS 13MHz OUTPUT *SLAVE OPERATION: BCLK MAY HAVE ANY NUMBER OF CYCLES > 17. MCLK/RCLK RATIO MUST BE EXACTLY 1625x.
Figure 3. Digital Audio Interface Timing--Voice Modes with Optional Vibe Data 32 ______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
I2S STEREO SERIAL-INTERFACE TIMING DIAGRAM (SLAVE MODE) VOICE SERIAL-INTERFACE TIMING DIAGRAM (SLAVE MODE)
SDIN (INPUT) tHD tSU BCLK (BCI = 1, INPUT) BCLK (BCI = 0, INPUT) tDLY tBCLKH tf, tr tHD tSU tBCLKL
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Figure 4. Digital Audio Interface Timing Diagrams
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Changing Serial Audio Interface Modes
Set S1SD0 = S1SDI = 0 (register 0x03 and 0x05, bit B6) before making any mode changes to serial audio interface S1 to ensure proper operation. Similarly, set S2SD0 = S2SDI = 0 before making any mode changes to serial audio interface S2. This will disable the serial interface and ensure that sampling rate and filtering changes are made properly. Once the desired mode has been selected through I2C, the interface can be reenabled. Failure to observe this procedure can result in the MAX9851/MAX9853 being placed in an invalid operational mode, leading to unexpected results. any combination of the four channels of data from the S1 left/right and S2 left/right signal sources using the MIXDAL/R bits (register 0x08). Digital signals from the two interfaces in the 8kHz to 48kHz sample rate range are combined regardless of S1 and S2 interfaces modes, even if asynchronous with respect to each other or MCLK (in DAC-only mode). When operating in standard stereo audio mode, the input data stream from each interface is passed through separate 8x FIR interpolating filters. When operating in voice mode, the primary interface makes use of an interpolating IIR voiceband filter with an optional highpass component. When operating in mono mode, or when serial input data is disabled for a digital audio interface, the unused digital-signal processing filter paths are disabled to minimize supply-current consumption. The stereo signals at the left and right DAC may be additionally filtered in any mode with a programmable highpass filter to band limit the audio output and block DC. Set DHPL and DHPR (register 0x07, bits B3-B0) to 01, 10, or 11 to select one of the three highpass filter cutoff frequencies as shown in Table 2.
Powering On/Off the MAX9851/MAX9853
The MAX9851/MAX9853 power on in low-power shutdown mode with all signal paths disabled. It is good practice to configure all I2C registers except S1SDI and S2SDI (register 0x03 and 0x05, bit B6) before taking the MAX9851/MAX9853 out of shutdown. This may include setting initial volume levels, DAC and ADC modes of operation, stereo or mono operation, and audio interface settings. The analog section of the MAX9851/MAX9853 must be fully operational before the digital circuitry will function. Enable the charge pump by setting CPEN = 1 (register 0x1A, bit B4). Once the MAX9851/MAX9853 have been properly configured, set the global shutdown bit, SHDN, to 1 (register 0x1A, bit B7). The MAX9851/MAX9853 are fully operational 70ms after SHDN is set. Finally, if the DACs are to be used, program S1SDI and S2SDI as desired to enable DAC soft-start. Disable the audio outputs before powering down the MAX9851/MAX9853 by setting HRMODE and SPMODE (LOMODE) bits (Register 0x18). Ramping the volume to maximum attenuation is recommended before disabling the output amplifiers. Disable the headphone and speaker (or line outputs) once the audio is fully attenuated. The headphone and speaker (or line outputs) can be disabled within 50s of attenuation without any audible clicks or pops. Place the MAX9851/MAX9853 in shutdown after the outputs are disabled.
Table 2. DAC Highpass Filter Modes
DHPL/DHPR BIT SETTINGS 00 01 10 11 FILTER MODE No filtering 55Hz to 91Hz cutoff frequency 171Hz to 279Hz cutoff frequency 327Hz to 533Hz cutoff frequency
Sigma-Delta ADC
Set ADCLEN and ADCREN to 1 (register 0x1B, bit B5 and B4) to enable the MAX9851/MAX9853's stereo ADCs. The ADCs accept analog signals from the line inputs and the microphone inputs which can be mixed as described in the Signal Routing section prior to conversion. For ADC operation, program the enabled digital audio interface(s) to operate in master mode so that the sampling clock is generated within the MAX9851/MAX9853. The maximum signal that will not clip the ADC input is 2VP-P. If clipping does occur, reduce the microphone or line input gain as appropriate. Clipping in the digital circuitry is indicated by CLD (register 0x00, bit B7).
Sigma-Delta DAC
Set DACLEN and DACREN to 1 (register 0x1B, bit B7 and B6) to enable the left and right DACs while the S1SDI and S2SDI bits are cleared and the SLD status bit is low to ensure click/pop suppression, then enable S1SDI and S2SDI as desired. The stereo DACs can mix
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Internal Timing
The MAX9851/MAX9853 operate from either a 13MHz or 26MHz master input clock (MCLK). 16kHz voice mode requires a 26MHz clock. The quality of the clock signal has a direct relationship with the dynamic range performance of the data converters. Clock jitter below 100psRMS is necessary to maintain maximum performance figures. The MAX9851/MAX9853 make extensive use of MCLK for all chip functions. The digital circuitry and Class D amplifiers require a master clock to operate. Once the MAX9851/MAX9853 are initialized, MCLK is not required during modes where the ADC and DAC are disabled (for instance, playing line inputs through the headphone outputs). However, MCLK needs to be applied for a short period of time (> 1ms) after power-on to initialize volume control circuitry--this is only once per power-on. See the Typical Operating Characteristics for filter characteristics.
MAX9851/MAX9853
Line Inputs
The MAX9851/MAX9853 provide two single-ended audio line inputs for mixing with analog audio from either the ADC record path or to the DAC playback path. Each line input amplifier has a programmablegain function controlled by PGAL1 and PGAL2 (registers 0x0E and 0x0F). The gain is adjustable over the +30dB to -32dB range in 2dB increments.
DirectDrive Headphone and Receiver Amplifiers
The MAX9851/MAX9853 headphone and receiver amplifiers make use of Maxim's patented DirectDrive architecture to create ground-biased outputs as shown in Figure 5. Traditional single-supply headphone amplifiers have their outputs biased about a nominal DC voltage, typically half the supply. Large coupling capacitors are typically needed to block this DC bias from the headphone. Without these capacitors, a significant amount of DC current flows to the headphone, resulting in unnecessary power dissipation and possible damage to both headphone and headphone amplifier. The DirectDrive architecture uses a charge pump to create an internal negative supply voltage. This allows the MAX9851/ MAX9853 headphone and receiver outputs to be biased about ground, almost doubling the dynamic range while operating from a single supply. With no DC component, there is no need for the large DC-blocking capacitors. Instead of two large (33F to 330F) capacitors, the MAX9851/MAX9853 charge pump requires only two small ceramic capacitors (0.22F and 1F), conserving board space, reducing cost, improving the frequency response, and THD of the headphone amplifier. In addition to the cost and size disadvantages, the DC-blocking capacitors required by conventional headphone amplifiers limit low-frequency response and decrease PSRR performance. Some dielectrics can significantly distort the audio signal.
Voiceband Filters
The MAX9851/MAX9853 provide mono voiceband filtering for both output and input digital audio signals on the primary interface. Set ABPE to 1 (register 0x07, bit B5) to enable the highpass component of the voiceband filtering on the output of the ADC. Similarly, set DBPE to 1 (register 0x07, bit B4) to enable the highpass component of the voiceband filtering for incoming data on the primary digital audio interface. Voiceband filtering is available on either interface for outgoing digital audio from the ADC, and incoming data only on the primary S1 digital audio interface. The voiceband filters only operate when the MAX9851/MAX9853 are configured in voice mode. The DAC and ADC voiceband filters are identical, with sample-rate-specific corner frequencies. Operating in 8kHz voice mode, the filter passband extends from 130Hz to 3.5kHz. In 16kHz voice mode, the filter passband extends from 260Hz to 7kHz. Stopband attenuation is greater than 28dB for low frequency and 75dB for high frequencies and the lowpass cutoff frequency is below fS / 2.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
VDD
Class D Speaker Amplifiers (MAX9851 Only)
Set SPMODE to 11 (register 0x18, bits B4 and B3) to enable the stereo speaker amplifier of the MAX9851. SPMODE can be optionally set to enable just the left or the right speaker. CPCLK (register 0x1A, bit B0) must be set to 1 to ensure proper Class D amplifier operation. The Class D amplifier oscillator is derived from MCLK. MCLK must be enabled for proper Class D amplifier operation. The on-board filterless, low-EMI, Class D audio power amplifier offers Class AB performance with Class D efficiency. The amplifiers are powered directly from the battery (PVDD) for maximum efficiency and power output. A typical output power of up to 2W per channel allows powering of internal speakers without the need for a separate power amplifier IC. The Class D amplifier has been optimized for efficiency and greatly reduced EMI. The output gain is adjustable between +13.1dB and -66.4dB. The gain of the speaker amplifier is controlled with SPVOLL and SPVOLR (registers 0x16 and 0x17, bits B0-B5). Efficiency Rather than using a traditional Class AB speaker amplifier, the MAX9851 uses a high-efficiency Class D audio amplifier to provide speaker outputs. The MAX9851 uses Maxim's unique, patented modulation scheme that eliminates the LC filter required by standard Class D amplifiers, improving efficiency, reducing component count, and conserving board space and system cost. Conventional Class D amplifiers output a 50% duty-cycle square wave when no signal is present. With no filter, the square wave appears across the load as a DC voltage, resulting in finite load current, increasing power consumption. When no signal is present at the input of the MAX9851, the outputs switch in-phase at a low duty cycle. Because the MAX9851 drives the speaker differentially, the two outputs cancel, resulting in no net voltage across the speaker, minimizing power consumption. Filterless Operation Proprietary active emissions limiting (AEL) output stage circuitry allows the amplifier to operate at switching frequencies above 1MHz while still providing at least 20dB margin below FCC-radiated emissions limits. Set CPCLK = 1 (register 0x1A, bit B0) to configure the Class D amplifier to operate with a 1.1MHz MCLK derived switching frequency. The MAX9851 does not require an output filter, instead relying on the inherent
VDD / 2
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Figure 5. Traditional Amplifier Output vs. MAX9851/MAX9853 DirectDrive Output
Set HRMODE to 100 (register 0x18, bits B2-B0) to enable standard stereo headphone mode. Set HRMODE to 110 to configure balanced mono operation and 101 for single-ended mono operation. When operating in balanced mode, the right headphone amplifier is reconfigured as a slave amplifier to create a bridgetied load output. In single-ended mono mode, only the left headphone amplifier is used. Both mono modes output the sum of the left- and right-channel audio. Set HRMODE to 111 to disable the headphone amplifier and enable the mono receiver amplifier. The receiver amplifier outputs a sum of the left and right headphone signals to provide 100mW to a telephone earpiece speaker. The headphone/receiver amplifiers have programmable gain controlled by HRVOLL and HRVOLR (registers 0x14 and 0x15). The independent gain control offers a range of +5.5dB to -74dB.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
inductance of the speaker coil to filter the high-frequency PWM components, and the natural filtering of both the speaker and the human ear to recover the audio component of the square-wave output. Eliminating the output filter results in a smaller, less costly, and more efficient solution. Because the switching frequency of the MAX9851 output is well beyond the bandwidth of cell-phone speakers, voice coil movement due to the square-wave frequency is negligible. (for instance, playing line inputs through the headphone outputs). However, the part needs MCLK to be applied for a short period of time (> 1ms) after poweron to initialize volume control circuitry--this is only once per power-on.
MAX9851/MAX9853
Microphone Amplifiers
Two microphone interfaces allow the MAX9851/ MAX9853 to accommodate inputs from both an internal handset microphone and external headset microphones. Both inputs feature 0 to +20dB of gain selectable in 1dB increments with an additional 20dB of gain selectable to increase the range from 0 to +40dB, accommodating a wide range of microphones. Set MEXT to 0 (register 0x12, bit B2) to select the internal microphone input, featuring a differential input to minimize noise pickup. A low-noise bias voltage (INTMICBIAS) is available to bias the microphone from a clean supply. The mono input signal is treated as a left microphone signal by MAX9851/MAX9853 internal circuitry. Bypass INTMICBIAS to GND with a 1F capacitor. Set MEXT to 1 to select the external microphone input featuring stereo single-ended inputs with a separate ground to reduce noise pickup. Connect the external microphones to EXTMICBIASL and EXTMICBIASR to provide a bias voltage for the microphones. Set RBIAS to 0 (register 0x12, bit B0) to select an output impedance of 2.2k for the independent low-noise bias pins. Alternatively, set RBIAS to 1 to select an output impedance of 470. A microphone bias voltage of +2.4V, generated from INTMICBIAS, is used for both resistor settings. The selectable bias resistors allow extra flexibility in selecting microphones without requiring external resistors to bias the microphones. The 470 impedance can be chosen when using an external RC filter near the headset jack. The external biases are high impedance when disabled, even in the presence of an applied voltage up to AVDD.
Differential Line Outputs (MAX9853 Only)
The MAX9853 features a pair of differential line outputs instead of the Class D speaker amplifiers of the MAX9851. Set LOMODE to 11 (register 0x18, bits B4 and B3) to enable the stereo line outputs of the MAX9853. The line outputs can be used simultaneously with the headphone or receiver amplifier for maximum flexibility in driving an external audio amplifier or other analog audio IC. The line outputs feature gain adjustable between +7.1dB and -72.4dB. Program the gain of the line outputs with LOPGAL and LOPGAR (registers 0x16 and 0x17, bits B5 to B0). Shutdown Output and Fault Input Shutdown output and fault input pins are available for interfacing with an external speaker amplifier IC. The open-drain shutdown output can be used to control an external amplifier through the MAX9853 I2C interface. The fault logic input has an internal 300k pullup resistor which can be reported in the I2C status register and trigger the interrupt output.
Volume Control
The MAX9851/MAX9853 feature volume control amplifiers on the headphone, receiver, speaker (MAX9851 only), and line (MAX9853 only) outputs that can be controlled through the I2C interface. Each output has separate volume control amplifiers for left and right in addition to a mute feature. Set VSEN to 1 (register 0x18, bit B6) to enable volume change smoothing. Enabling this feature gives a smooth-sounding gain change by stepping through all intermediate settings at a 2ms rate per step when a volume or mute change occurs. Set ZDEN to 1 (register 0x18, bit B5) to enable the zerocrossing detection feature. This causes volume and mute changes to occur only at zero-crossings of the audio waveform and reduces objectionable clicks or "zipper noise" that can occur while making volume changes. Once the part is initialized, the MCLK is not required during modes where the ADC and DAC are disabled
Sidetone
An internally routed sidetone signal is available to allow analog routing of the left microphone signal. The sidetone input is the output of the left microphone gain amplifier. This sidetone signal has an independent gain adjustment from -32dB to +30dB. The sidetone signal is available as an input to both the left and right analog output mixer (see the Signal Routing section).
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
VIBE Output
The MAX9851/MAX9853 include a VIBE digital output that may be used to control an external vibrator/transducer, or may be used as a general-purpose output. The Vibe circuitry module has its own multiplexer to allow it to operate from either the S1 or S2 digital audio interface. Set TSEL to 0 (register 0x09, bit B5) to derive the VIBE output from the primary digital audio interface right channel. Set TSEL to 1 to derive the VIBE output from the secondary digital audio interface left or monomixed left and right channels. When using signal data to drive VIBE, programmable gain set by TGAIN (register 0x19, bits B7-B4) is used to make adjustments with 10-bit output resolution. A digital lowpass filter is used to condition the signal for use at the VIBE output. The VIBE output signal may be generated using either a threshold comparison of a rectified signal or by an oversampled 1-bit DAC conversion of a nonrectified signal. Set TMUX to 11 (register 0x09, bits B7-B6) to use the output of the internal sigma-delta converter for driving the transducer output. Set TMUX to 10 to compare the digital audio signal to a programmable squelch threshold level and generate an output signal as shown in Figure 6. When driving an external transducer use an external lowpass filter as shown in Figure 7. The VIBE signal can be amplified if needed by an external amplifier. Set TMUX to 00 or 01 to force the output to a fixed 1 or 0, respectively, when using VIBE as a general-purpose output. Use a 1k pullup resistor to DVDD to achieve a full-scale signal from the opendrain output.
COMPARATOR OUTPUT SIGNAL
COMPARATOR SQUELCH LEVEL
INPUT SIGNAL
Figure 6. VIBE Output Using Comparator
S1 RIGHT S2 LEFT+RIGHT DVDD 0 TSEL -30dB TO +30dB 400Hz LOWPASS FILTER 5-BIT SQUELCH LEVEL 1 10k
TMUX VIBE
TRANSDUCER VIBE
PGA
1-BIT DAC
Figure 7. Transducer/Vibe Functional Diagram 38 ______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Signal Routing
The MAX9851/MAX9853 feature extensive signal-path mixing, allowing nearly any combination of inputs and outputs. DAC Inputs Use MIXDAL and MIXDAR (register 0x08-see the I2C Registers and Bit Descriptions section for detailed register definitions) to configure the digital mixer at the input of each DAC. The mixer allows signals from each digital audio interface to be mixed prior to conversion, regardless of sampling rate and synchronization. Each left and right data stream can be routed independently to either the left or right DAC to allow for swapping of the left and right channels and any possible combination of digital signals. Audio Outputs Configure MXOUTL and MXOUTR (register 0x0B-see the I2C Registers and Bit Descriptions section for detailed register definitions) to adjust the analog output mixer. This mixer combines signals prior to the analog output stages: consisting of the headphone amplifier, receiver amplifier, and speaker or line amplifiers. Each line input, in addition to the analog sidetone, can be mixed with the left or right DAC output prior to amplification. ADC Inputs Use MXINL and MXINR (register 0x0A-see the I 2C Registers and Bit Descriptions section for detailed register definitions) to configure the ADC mixer. Each ADC has the option of converting the left microphone signal, the right microphone signal, and each of the line inputs. This allows for maximum flexibility when recording input signals. ister 0x1A, bit B4) to turn on the charge pump. The negative charge-pump voltage is established and the audio outputs are ready for use approximately 70ms after CPEN is set to 1. The state of CPCLK (register 0x1A, bit B0) determines whether the charge-pump oscillator is derived from the internal 650kHz oscillator or from the MCLK. Set LFEN = 1, CPEN = 1 and set CPCLK = 0 (register 0x1A, Bits B5, B4 and B0) to enable the charge pump using the internal oscillator. The charge pump runs independent from MCLK when the internal oscillator is enabled allowing the charge pump to operate when the DAC is disabled or when only the line inputs are used. Set CPCLK = 1 to synchronize the charge pump with the MCLK. The switching frequency of the charge pump is well beyond the audio range and does not interfere with audio signals. The switch drivers utilize techniques that minimize noise generated by turn-on and turn-off transients. Although not typically required, additional high-frequency noise attenuation can be achieved by increasing the size of C2 and the CPVDD bypass capacitor (see the Functional Diagrams/Typical Operating Circuits).
MAX9851/MAX9853
Headset Detect
The MAX9851/MAX9853 feature comprehensive headset detection to accommodate a wide variety of headsets. Two operating modes are provided: one for wake-up upon headset insertion and one for detecting the configuration of the headset in use. While in sleep mode, the detection circuitry can be used to detect the insertion of a headset and trigger a hardware interrupt. In this mode, the circuitry can be powered directly from the battery using minimal power. When a headset is inserted, the microcontroller (C) can detect the hardware interrupt and bring the system out of low-power standby. The C can then determine the configuration of the inserted headset and appropriately configure the MAX9851/MAX9853. Figure 8 shows the headset detection circuitry.
Charge Pump
The DirectDrive headphone and receiver outputs of the MAX9851/MAX9853 require a charge pump to create an internal negative power supply. Set CPEN = 1 (reg-
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
VINTMICBIAS
MAX9851 MAX9853
EXTMICBIASR AVDD AGND AVDD 10% EXTMICR HPL 80% VINTMICBIAS EXTMICL 80% I2C REGISTER 0x01 B5-B0 95%
HPR
EXTMICBIASL
95%
SLEEP MODE
IRQ CONTROL
IRQ
10%
Figure 8. Headset-Detection Circuitry
Power-Off/Sleep Mode When the analog or digital supplies are removed from the MAX9851/MAX9853, the headset detect circuit enters sleep mode (PVDD must remain powered, typically through a direct connection to the battery). Alternatively, set SLEEP = 1 (register 0x19, bit B2) to allow sleep mode to monitor headset insertion and removal while the MAX9851/MAX9853 are in low-power shutdown. In this mode, the external headset jack is monitored for activity, but no attempt is made to detect the headset configuration. For proper operation, the battery voltage must be available, through PVDD. A low-current bias is supplied to EXTMICBIASL to allow detection of activity. If this pin is pulled low at any time, a hardware interrupt is triggered and IRQ is set. IRQ remains asserted until sleep mode is exited or the headset jack is removed. Any pullup resistor on the open-drain IRQ output will cause a small current to be drawn until the C can initiate a power-up sequence. Once power is applied to the MAX9851/MAX9853, or SLEEP is set to 0, the sleep mode is disabled and normal headset detect functions can be used. In sleep mode it is important that the microphone bias be disabled by setting RBEN to 0, and that no parasitic
diodes load the EXTMICBIASL/R pins. Also note that the autodetect circuitry will trigger IRQ for approximately 50ms when PVDD is initially applied or when sleep mode is first enabled. This is a consequence of the weak pullup current used to sense EXTMICBIASL and the attached AC-coupling capacitor that must be charged. Normal Operation Set ENA to 1 (register 0x19, bit B3) and HSTEST to 01 (register 0x19, bits B1-B0) to enable normal operation. In this mode EXTMICBIASL, EXTMICBIASR, HPL, and HPR are probed to determine the loading of each pin. The detected loading is then reported in the HSDET bits (status register 0x01 B5-B0). The loading of each pin is shown in Table 3 along with the reported HSDET code. The headset configuration that corresponds to some possible loading states is shown in Table 4. Headphone detection is done in a two-step process. Test 1 (HSTEST = 01) is used to determine if stereo headphones are connected. If a balanced mono headphone is connected, this test will be inconclusive. Test 2 (HSTEST = 10) must then be performed to determine the configuration. See Figure 9 for the typical headphone test procedure.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 3. HSDET Bit Decode
HSDET [11XXXX] [01XXXX] [00XXXX] [XX1XXX] [XX0XXX] [XXX1XX] [XXX0XX] [XXXX11] [XXXX01] [XXXX00] HPR x x x Low High x x x x x HPL x x x x x Low High x x x EXTMICBIASL Low Mid High x x x x x x x EXTMICBIASR x x x x x x x Low Mid High
Table 4. Example Headset Configurations
HEADSET CONFIGURATION No External Connector 3-Pole Connector Mono HP, Mono Microphone 4-Pole Connector Stereo HP, Mono Microphone Mono HP, Stereo Microphone 5-Pole Connector Stereo HP, Stereo Microphone Test 2 Only* No HP Mono Balanced HP Mono Balanced HP, Mono Microphone Mono Balanced HP, Stereo Microphone Low Low Low Low High Low Low Low X X Mid Mid X X High Mid Low Low Mid Mid Low Low Low High Mid Mid High Mid Low High Mid High HPR High HPL High EXTMICBIASL High EXTMICBIASR High
*Test 2 is to be performed after Test 1 finds HPR and HPL High. Test 2 is needed only to determine if a balanced mono speaker is connected to HPR and HPL.
Microphone detection is provided by the microphone bias circuitry. Set RBEN, MICLEN, and MICREN to 1 (register 0x12, bit B1 and register 0x1B, bits B1 and B0) to enable the microphone bias circuitry. The microphone bias voltage is compared with two thresholds, 95% and 10% of VINTMICBIAS. The thresholds define three output-impedance states: high, medium, and low. The high-impedance state occurs when there is no load on the EXTMICBIAS pins. The medium state occurs when the load is an electret module or an amplified microphone biased at midsupply. The low state occurs when the microphone pin is shorted to AGND by a hook switch or an accessory logic/identification pin.
Alternatively, hook switches that disconnect the microphone can be detected by looking for the high state. Headphone detection is accomplished by placing a small pullup current on HPL and HPR. For proper headphone detection, make sure that the headphone amplifiers are disabled. Set HSTEST to 01 (register 0x19, bit B1 and B0) to enable headphone Test 1 (see Table 5). The sense bias for the headphone pins attempts to pull both HPL and HPR up to AVDD with a low current to avoid creating an audible disturbance on the headphones. When a stereo headphone is connected, both HPR and HPL are pulled low. When no headphone is connected, or a balanced mono speaker has been
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
connected, HPR and HPL are pulled high by the internal sense bias. To detect the balanced mono configuration, set HSTEST to 10 to enable Test 2. Test 2 connects a small pulldown current to HPR and a pullup to HPL. A balanced mono speaker will result in HPL pulled low whereas an open circuit would still allow HPL to be pulled high by AVDD. Attempting to detect the headphone configuration while the amplifiers are active will lead to erroneous results as the outputs of the active headphone amplifiers are biased at 0V. In normal headset detect mode, the removal or insertion of a jack, as monitored by EXTMICBIASL, triggers an interrupt on the IRQ pin. The state changes that trigger an interrupt are shown in Table 6. Alternatively, set IHSD = 1 (register 0x02, bit B1) to cause all changes in the HSDET bits to trigger an interrupt. Changes to HSDET are digitally debounced with a 20ms filter.
Interrupt Output
Hardware interrupts are reported on the MAX9851/ MAX9853 open-drain IRQ pin. The interrupt pin can be triggered by the sources shown in Table 7. When an interrupt occurs, IRQ remains low until the interrupt is serviced by reading the status register 0x00. If an interrupt occurs, it will be reported only if the corresponding interrupt enable is set in register 0x02 (see the I 2 C Registers and Bit Descriptions section for detailed register definitions).
Table 5. Headphone Detect Test Modes
HSTEST(1:0) 00 01 10 11 CONFIGURATION Headphone sense bias disconnected Headphone sense test 1 (standard headphone detection) Headphone sense test 2 (balanced mono headphone detection) Reserved
Table 6. Headset Pin Changes Causing Hardware Interrupts
PIN-STATE CHANGE EXTMICBIASL: high EXTMICBIASL: mid EXTMICBIASL: low EXTMICBIASL: low low or mid low mid high DESCRIPTION Headset inserted Hook switch pressed Hook switch released Headset removed
Table 7. Sources of Hardware Interrupts
ACTIVATE HEADSET DETECT CIRCUITRY
INTERRUPT SOURCES Clip Detect Slew Level Detect Digital PLL UnLock Headset Configuration Change Headset Removal and Insertion Speaker/External Fault
MASKABLE IN REGISTER (0x02) Yes Yes Yes Yes No Yes
PERFORM HEADPHONE SENSE TEST 1
HPR AND HPL
HIGH
PERFORM HEADPHONE SENSE TEST 2
LOW
HIGH HPL LOW
STEREO HEADPHONES
BALANCED MONO HEADPHONES
NO HEADPHONES
Figure 9. Headphone Detection Procedure
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
I2C Registers and Bit Descriptions
Twenty-eight internal registers program and report the status of the MAX9851/MAX9853. Table 8 lists all of the registers, their addresses, and power-on-reset states. Registers 0x00 and 0x01 are read-only while all of the other registers are read/write. Registers 0x1C-0x1F are reserved for factory testing. Write zeros to all unused bits in the register table when updating the register, unless otherwise noted Slave Address The MAX9851/MAX9853 are preprogrammed with a slave address of 0x20 or 0010000. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX9851/MAX9853 to read mode. Set the read/write bit to 0 to configure the MAX9851/ MAX9853 to write mode. The address is the first byte of information sent to the MAX9851/MAX9853 after the START condition.
MAX9851/MAX9853
Table 8. Register Map
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS POWER -ON RESET STATE
STATUS Status 0 Status 1 Interrupt Enable DIGITAL AUDIO S1 Interface Mode Interface Mode Interface Mode Interface Mode DIGITAL FILTERS Filter Modes DIGITAL MIXERS DAC-L/R Mixer TRANSDUCER/VIBE T-DAC MUX/ Squelch ANALOG MIXERS ADC Input Mixers Audio Output Mixers AUDIO GAIN Audio Interface S1 Gain Audio Interface S2 Gain Line1 Input Gain Line2 Input Gain 0 0 0 0 0 0 PGADS1 PGADS2 PGAL1 PGAL2 0x0C 0x0D 0x0E 0x0F 0x00 0x00 0x00 0x00 MXINL MXOUTL MXINR MXOUTR 0x0A 0x0B 0x00 0x00 TMUX TSEL VTH 0x09 0x00 MIXDAL MIXDAR 0x08 0x20 MHZ ADCDC ABPE DBPE DHPL DHPR 0x07 0x70 S1SDO S1MAS S2SDO S2MAS S1SDI S1WCI S2SDI S2WCI S1MNO S1BCI S2MNO S2BCI 0 0 0 0 S2DLY 0 S1DLY 0 S2MODE 0 S2WS S1MODE 0 S1WS 0x03 0x04 0x05 0x06 0x00 0x00 0x00 0x00 CLD AOK ICLD SLD 1 ISLD IULK 0 0 ULK 0 0 HSDET 0 IHSD IFAULT 0 HSD FAULT 0x00 0x01 0x02 -- -- 0x00
DIGITAL AUDIO S2
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 8. Register Map (continued)
REGISTER B7 B6 B5 B4 B3 B2 B1 B0 REGISTER ADDRESS POWER -ON RESET STATE 0x00 0x00
Microphone L Input Gain Microphone R Input Gain MICROPHONE Microphone Mode AUDIO VOLUME Sidetone Volume Headphone/ Receiver Volume Left Headphone/ Receiver Volume Right Left Speaker Volume1 or Line Output Gain2 Right Speaker Volume1 or Line Output Gain2 AUDIO OUTPUT Audio Output Mode
0 0
0 0
PALEN PAREN
PGAML PGAMR
0x10 0x11
0
0
0
0
MMIC
MEXT
RBEN
RBIAS
0x12
0x00
0 0
0 HRMUT
0
PGAS HRVOLL
0x13 0x14
0x00 0x00
0
0 SPMUT1 or LOMUT2
HRVOLR
0x15
0x00
0
SPVOLL1 or LOPGAL2
0x16
0x00
0
0
SPVOLR1 or LOPGAR2
0x17
0x00
0
VSEN
ZDEN
SPMODE1 or LOMODE2
HRMODE
0x18
0x00
VIBE/HEADSET DETECT T-DAC PGA/HSET Detect SYSTEM System SHUTDOWN Audio Shutdown
1MAX9851 2MAX9853
TGAIN
ENA
SLEEP
HSTEST
0x19
0x00
SHDN
DACLEN
HFEN
DACREN
LFEN
ADCLEN
CPEN
ADCREN
0
DATEN
1
0
0
MICLEN
CPCLK
MICREN
0x1A
0x1B
0x00
0x00
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Status Registers (0x00, 0x01)
Table 9. Status Register 0
REG 0x00 B7 CLD B6 SLD B5 ULK B4 0 B3 0 B2 0 B1 HSD B0 FAULT
Bits in status registers 0x00 and 0x01 are set when an alert condition exists. The status bits are only updated if the corresponding interrupt enable is set in register 0x02. All bits in status register 0x00 are automatically cleared upon a read operation of the register and will be set again if the condition remains or occurs following the read of this register. Clip Detect Flag (CLD) 1 = DAC or ADC clipping has occurred. 0 = No clipping has occurred. CLD reports that the DAC input data or ADC output data is clipping due to an excessive signal amplitude in the digital signal path at any one of seven locations: DAC mono mixer (left or right), DAC modulator (left or right), ADC path highpass filter (left or right), or the VIBE path modulator. To resolve a clip condition in the signal path, the DAC gain settings and analog input gain settings should be lowered. As the CLD bit does not indicate where the overload has occurred, identify the source by lowering gains individually. Slew Level Detect Flag (SLD) 1 = Volume slewing complete. 0 = No volume slewing sequences have completed since the status register was last read. SLD reports that any one of the programmable-gain arrays or volume controllers has completed slews from a previous setting to a new programmed setting. If multiple gain arrays or volume controllers are changed at the same time, in either the analog or digital domain, SLD flag will be set after the last slew adjusting in each domain. SLD also reports when the serial interface softstart or soft-stop process has completed.
Digital PLL Unlock Flag (ULK) 1 = Either the S1 or S2 internal DAC PLL is not locked. 0 = Both the S1 and S2 internal PLLs are locked if enabled and operating properly. ULK reports that the digital audio phase-locked loop for either DAC became unlocked and input digital signal data is unreliable. Headset Configuration Change Flag (HSD) 1 = Headset configuration has changed. 0 = No change in headset configuration. HSD reports changes in HSDET (register 0x01, bits B5-B0). Regardless of the state of IHSD, any removal or insertion of a jack (detected by monitoring EXTMICBIASL) triggers an interrupt on the IRQ line. See the Headset Detect section. Changes on HSDET are digitally debounced with an approximate 20ms filter before setting HSD. Valid changes on HSDET are delayed by this amount. MCLK needs to be applied for a short period of time (> 1ms) after power-on to initialize this flag. MAX9851: Speaker Fault Flag (FAULT) 1 = Current overload has occurred on the speaker amplifiers. 0 = Current consumption is normal. For the MAX9851, FAULT indicates that the Class D output amplifiers have entered a current overload state. MAX9853: External Fault Flag (FAULT) 1 = The FAULTIN pin has been pulled low. 0 = FAULTIN pin high. For the MAX9853, FAULT indicates that the FAULTIN pin has been pulled low.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 10. Status Register 1
REG 0x01 B7 AOK B6 1 B5 B4 B3 HSDET B2 B1 B0
Analog Section OK (AOK) 1 = Analog circuitry operating properly. 0 = Analog startup not complete or the MAX9851/ MAX9853 are in shutdown. AOK reports that the analog section of the MAX9851/ MAX9853 is properly operating. When power is applied to MAX9851/MAX9853, the AOK bit is set to 0. The MAX9851/MAX9853 must be taken out of shutdown and the charge pump must be operating for this bit to be set
to 1. The digital signal processing sections of the MAX9851/MAX9853 do not operate unless this bit is 1. Headset Jack Mode Indicator (HSDET) HSDET reports the load impedance of the four headset test pins, EXTMICBIASL, EXTMICBIASR, HPL, and HPR, for use in determining the connected headset configuration. See Table 3 in the Headset Detect section for decoding the value of these bits.
Interrupt Enable Register (0x02)
Table 11. Interrupt Enables
REG 0x02 B7 ICLD B6 ISLD B5 IULK B4 0 B3 0 B2 0 B1 IHSD B0 IFAULT
Clip Detect Interrupt Enable (ICLD) 1 = Detection of clipping triggers a hardware interrupt and sets CLD (register 0x00, B7). 0 = Clipping not reported. Slew Detect Interrupt Enable (ISLD) 1 = Completion of a slewed volume change triggers a hardware interrupt and sets SLD (register 0x00, B6). 0 = Completion of slewing not reported. Digital PLL Unlock Interrupt Enable (IULK) 1 = An unlock condition in the internal PLLs trigger a hardware interrupt and sets ULK (register 0x00, B5). 0 = Unlock conditions not reported.
Headset Detect Interrupt Enable (IHSD) 1 = All changes in headset configuration trigger a hardware interrupt and set HSD (register 0x00, B1). 0 = Only jack insertions and removals are reported. If IHSD = 0 any removal or insertion of a jack (detected by monitoring EXTMICBIASL) will still trigger an interrupt on the IRQ line, but other HSDET bit changes will not. MAX9851: Speaker Fault Interrupt Enable (IFAULT) 1 = Current overload at the Class D speaker amplifier triggers a hardware interrupt and sets FAULT (register 0x00, B0). 0 = Current overload not reported. MAX9853: External Fault Interrupt Enable (IFAULT) 1 = Inputs on FAULTIN trigger a hardware interrupt and set FAULT (register 0x00, B0). 0 = Fault inputs not reported.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Audio Interface Registers (0x03, 0x04, 0x05, 0x06)
Table 12. Audio Interface S1
REG 0x03 0x04 0x05 0x06 B7 S1SDO S1MAS S2SDO S2MAS B6 S1SDI S1WCI S2SDI S2WCI B5 S1MNO S1BCI S2MNO S2BCI B4 0 0 0 0 S2DLY 0 S1DLY 0 S2MODE 0 S2WS B3 B2 S1MODE 0 S1WS B1 B0
Serial Data Output Enable (S1SDO/S2SDO) 1 = Digital audio output enabled. 0 = Digital audio output disabled. S1SDO/S2SDO = 1 configures the MAX9851/MAX9853 to route ADC output data to the respective audio interface output pin. S1SDO/S2SDO = 0 forces SDOUTS1/SDOUTS2 low. When both S1SDO and S2SDO are enabled, the S1 and S2 interfaces output the same data. If both outputs are enabled, the individual interfaces may be configured into different format modes as long as the programmed sample rates are identical. Serial Data Input Enable (S1SDI/S2SDI) 1 = Digital audio input enabled. 0 = Digital audio input disabled. S1SDI/S2SDI = 1 configures the MAX9851/MAX9853 to perform a soft-start sequence and transfer incoming audio data from the respective SDIN pin to the digital filters for that interface. S1SDI/S2SDI = 0 configures the MAX9851/MAX9853 to begin a soft-stop sequence and then disregard incoming audio data and disable the digital input filter path of that interface. The SLD (register 0x00, B6) flag is set when the softstart or soft-stop sequence completes. The S1SDI and S2SDI bits should be used to cleanly soft-stop signal data prior to changing the S1MODE or S2MODE bits. Soft-stop sequences take approximately 10ms to completely slew the volume from full scale to mute. Set the S1SDI/S2SDI bits to enable the DACs after DACLEN and DACREN (register 0x1B, bits B7 and B6) are set for clean startup transitions. Likewise, clear S1SDI/S2SDI before clearing DACLEN and DACREN. Serial Input Mono Mix Enable (S1MNO/S2MNO) 1 = Left and right digital input signals mixed to mono and output to the left channel. 0 = Stereo left and right digital signals maintained.
The mono signal is digitally filtered and interpolated through the left-channel digital filter while the right-channel digital filter is shut down. The output of the left-channel filter can be routed to either or both the left and right DACs. The stereo inputs are not attenuated before mixing to mono. Clipping can occur with large input signals. Interface S1/S2 Mode (S1MODE/S2MODE) S1MODE/S2MODE configures the MAX9851/MAX9853 for a specific audio sampling rate on the respective digital audio interface. Set S1MODE/S2MODE to 0x1 through 0x9 to configure the interface for stereo audio operation at the specified sample rate. Set S1MODE/S2MODE to 0xA or 0xB to configure the interface to operate in voice mode. The secondary digital audio interface is intended to be used primarily in modes 0x1 through 0x9 as voiceband filtering is available only on the primary serial interface. MCLK must be 26MHz when operating in 16kHz voice mode.
Table 13. Serial Interface Modes of Operation
S1 MODE/ S2 MODE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC, 0xD, 0xE, 0xF RATE (kHz) -- 8 11.025 12 16 22.05 24 32 44.1 48 8 16 -- MODE Interface off Stereo audio Stereo audio Stereo audio Stereo audio Stereo audio Stereo audio Stereo audio Stereo audio Stereo audio Mono voice mode Mono voice mode (MCLK must be 26MHz) Reserved
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Master Mode (S1MAS/S2MAS) 1 = Master mode (LRCLK and BCLK timing signals generated internally; LRCLK and BCLK configured as outputs). 0 = Slave mode (LRCLK and BCLK accepted from external source; LRCLK and BCLK configured as inputs). Slave mode timing signals may operate asynchronous to either the MCLK or the other audio interface source in DAC-only stereo audio modes. An interface with the ADC output enabled must operate in master mode, unless operating synchronously in voice mode. LRCLK Invert (S1WCI/S2WCI) 1 = Right-channel data is transmitted while LRCLK is low. 0 = Left-channel data is transmitted while LRCLK is low. Set S1WCI/S2WCI = 0 to conform to the I2S standard. S1WCI/S2WCI have no effect in voice mode. BCLK Invert (S1BCI/S2BCI) 1 = Digital audio bits are transferred on the falling edge of BCLK. 0 = Digital audio bits are transferred on the rising edge of BCLK. Set S1BCI/S2BCI = 0 to conform to the I2S standard. Data Delay (S1DLY/S2DLY) 1 = Digital audio MSB on SDIN and SDOUT is transferred on the 2nd BCLK edge following an LRCLK edge. 0 = Digital audio MSB on SDIN and SDOUT is transferred on the 1st BCLK edge following an LRCLK edge. Set S1DLY/S2DLY = 1 to conform to the I2S standard. S1DLY/S2DLY have no effect in voice mode. Word Size (S1WS/S2WS) 1 = 18-bit digital audio data. 0 = 16-bit digital audio data. When operating in master mode, the number of BLCK cycles per sample corresponds to the word size selected by S1WS/S2WS. S1WS/S2WS have no effect in voice mode. MCLK Frequency Mode (MHz) 1 = 26MHz MCLK. 0 = 13MHz MCLK. A 26MHz clock allows for synchronous 16kHz voice mode. All other modes of operation can operate from either MCLK frequency. ADC DC-Blocking Filter Enable (ADCDC) 1 = ADC DC block enabled. 0 = ADC DC block disabled. DC-blocking consists of a highpass filter with a cutoff frequency of fS / 1608. This filter is available in all modes of operation including voice modes. The ADC DCblocking filter can be overloaded with low-frequency signals with DC offset greater than 0.125V (one-eighth full scale). ADC Bandpass Filter Enable (ABPE) 1 = ADC bandpass filter enabled. 0 = ADC bandpass filter disabled. ABPE = 1 enables the ADC highpass filter in combination with the ADC lowpass filter to create a bandpass filter. The ADC voiceband filters only operate on the left output channel data of voiceband, the ADC, and when operating in voice mode. DAC Bandpass Filter Enable (DBPE) 1 = DAC bandpass filter enabled. 0 = DAC bandpass filter disabled. DBPE = 1 enables the DAC highpass filter in combination with the DAC lowpass filter to create a bandpass filter. The DAC filters only operate on the S1 left input or mono S1 L+R input signal data. Left and Right DAC Highpass Filter Mode (DHPL/DHPR) 00 = No filtering. 01 = 55Hz to 91Hz cutoff frequency. 10 = 171Hz to 279Hz cutoff frequency. 11 = 327Hz to 533Hz cutoff frequency. When both the ADC and DAC are enabled, the exact cutoff frequency of each setting depends on the sample rate in use. In DAC-only mode, the exact cutoff frequency will be the high end of the range above.
Digital Filter Register (0x07)
Table 14. Digital Filter
REG 0x07 B7 MHZ B6 B5 B4 B3 B2 B1 B0 ADCDC ABPE DBPE DHPL DHPR
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Digital Mixer Register (0x08)
Table 15. DAC Input Mixer
REG 0x08 B7 B6 MIXDAL B5 B4 B3 B2 MIXDAR B1 B0
Left and Right DAC Input Mixer (MIXDAL/MIXDAR) Table 16 shows the possible mixing configurations of the incoming digital audio streams. Each of the four
digital audio streams can be mixed in any combination and routed to the left or right DAC independently.
Table 16. DAC Input Mixer
INPUT SOURCE MIXDAL LEFT DAC (REGISTER 0x08, BITS B7-B4) XX1X XXX1 1XXX X1XX MIXDAR RIGHT DAC (REGISTER 0x08, BITS B3-B0) XX1X XXX1 1XXX X1XX DESCRIPTION Mix the primary digital audio interface left channel Mix the primary digital audio interface right channel Mix the secondary digital audio interface left channel Mix the secondary digital audio interface right channel
S1 Left S1 Right S2 Left S2 Right
X = Don't care.
Transducer/Vibe Register (0x09)
Table 17. Transducer/Vibe Bit Descriptions
REG 0x09 B7 TMUX B6 B5 TSEL B4 B3 B2 VTH B1 B0
Transducer/Vibe DAC Output Select (TMUX) 00 = VIBE is high. 01 = VIBE is low. 10 = Inverted threshold comparator output connected to VIBE. 11 = Inverted 1-bit DAC nonfiltered output connected to VIBE. See the VIBE Output section. TMUX selects the signal path of the VIBE output. Set TSEL (register 0x07, B5). Transducer/Vibe DAC Path Enable (TSEL) 1 = Secondary (S2) left or left + right digital audio signal. 0 = Primary (S1) right digital audio signal. TSEL = 0 configures the MAX9851/MAX9853 to use the right channel of the primary digital audio interface for
transducer/vibe signal conditioning. TSEL = 1 configures the MAX9851/MAX9853 to use the left channel (or left + right if S2 mono mix is enabled) of the secondary digital audio interface for transducer/vibe signal conditioning. Transducer/Vibe Squelch Comparator Threshold (VTH) When using the comparator for VIBE output, program VTH to set the level that positive digital audio data will be compared against. If the input data is less than VTH, then VIBE = 1. If the input data is greater than VTH, then VIBE = 0. If VTH = 0x00, all negative signal values will force VIBE high and all positive values will force VIBE low (see Figure 6 for operation).
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 18. Vibe Threshold
VTH 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 THRESHOLD VALUE 31/32 x FS 30/32 x FS 29/32 x FS 28/32 x FS 27/32 x FS 26/32 x FS 25/32 x FS 24/32 x FS 23/32 x FS 22/32 x FS 21/32 x FS 20/32 x FS 19/32 x FS 18/32 x FS 17/32 x FS 16/32 x FS VTH 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 THRESHOLD VALUE 15/32 x FS 14/32 x FS 13/32 x FS 12/32 x FS 11/32 x FS 10/32 x FS 9/32 x FS 8/32 x FS 7/32 x FS 6/32 x FS 5/32 x FS 4/32 x FS 3/32 x FS 2/32 x FS 1/32 x FS 0
Analog Mixer Registers (0x0A, 0x0B)
Table 19. Audio Mixer Bit Descriptions
REG 0x0A 0x0B B7 B6 MXINL MXOUTL B5 B4 B3 B2 MXINR MXOUTR B1 B0
Left and Right ADC Input Mixer (MXINL/MXINR)
Table 20. ADC Input Mixer
INPUT SOURCE Line 1 Line 2 Left Microphone Right Microphone MIXINL LEFT ADC (REGISTER 0x0A, Bits B7-B4) 1XXX X1XX XX1X XXX1 MIXINR RIGHT ADC (REGISTER 0x0A, Bits B3-B0) 1XXX X1XX XX1X XXX1 DESCRIPTION Mix line input 1 Mix line input 2 Mix the left microphone input Mix the right microphone input
X = Don't care.
Table 20 shows the possible mixing configurations of the analog input signals at the ADC. Each of the four input signals can be routed to either the left or right ADC independently in any combination. The ADC will
provide erroneous results if the microphones are selected as a mixer input while the microphone circuit is not enabled.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Left and Right Audio Output Mixer (MXOUTL/MXOUTR)
MAX9851/MAX9853
Table 21. Analog Output Mixer
INPUT SOURCE MXOUTL LEFT AUDIO OUTPUT (REGISTER 0x0B, BITS B7-B4) 1XXX X1XX XX1X XXX1 XXXX MXOUTR RIGHT AUDIO OUTPUT (REGISTER 0x0B, BITS B3-B0) 1XXX X1XX XX1X XXXX XXX1 DESCRIPTION
Sidetone Line 1 Line 2 Left DAC Output Right DAC Output
Mix the sidetone Mix line input 1 Mix line input 1 Mix the left DAC output to the left analog output Mix the right DAC output to the right analog output
X = Don't care.
Table 21 shows the possible mixing configurations of the analog audio output mixer. The sidetone, line 1, and line 2 signals can be routed to either the left or right
audio output in the combinations shown in Table 21. The left DAC output is only available on the left audio output and similarly for the right DAC output.
Audio Gain Control Registers (0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11)
Table 22. Digital Audio Input Gain Bit Descriptions
REG 0x0C 0x0D B7 B6 B5 B4 PGADS1 PGADS2 B3 B2 B1 B0
Programmable-Gain Adjustment for Digital Audio Inputs (PGADS1/PGADS2) PGADS1/PGADS2 configures the gain adjustment for the digital audio interface inputs. Code 0x00 is full signal
while 0xFF is full attenuation. This programmable-gain adjustment follows the mono mixers. Table 23 shows simplified gain control settings for digital signal inputs.
Table 23. Digital Audio Input Gain Settings
PGADS1/ PGADS2 0x00 0x0E 0x1C 0x29 0x35 0x40 0x4A 0x55 0x5E 0x67 0x70 0x78 0x7F 0x86 SETTING (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 PGADS1/ PGADS2 0x8D 0x93 0x99 0x9F 0xA5 0xAA 0xAE 0xB3 0xB7 0xBB 0xBF 0xC2 0xC6 0xC9 SETTING (dB) -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 PGADS1/ PGADS2 0xCC 0xCF 0xD2 0xD4 0xD6 0xD9 0xDB 0xDD 0xDF 0xE1 0xE2 0xE4 0xE5 0xFF SETTING (dB) -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 Mute
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 24. Line Input Gain Bit Descriptions
REG 0x0E 0x0F B7 0 0 B6 0 0 B5 0 0 B4 B3 B2 PGAL1 PGAL2 B1 B0
Programmable-Gain Adjustment for Line Inputs (PGAL1/PGAL2) PGAL1/PGAL2 configures the programmable-gain adjustment setting for line input 1/line input 2. Code
0x00 is maximum gain while 0x1F is maximum attenuation. Table 25 lists the gain setting for each code.
Table 25. Line Input Gain Control Settings
PGAL1/PGAL2 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 SETTING (dB) +30 +28 +26 +24 +22 +20 +18 +16 +14 +12 +10 +8 +6 +4 +2 0 -2 PGAL1/PGAL2 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F -- SETTING (dB) -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32 --
Table 26. Microphone Input Gain Bit Descriptions
REG 0x10 0x11 B7 0 0 B6 0 0 B5 PALEN PAREN B4 B3 B2 PGAML PGAMR B1 B0
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Programmable-Gain Adjustment for Microphone Sources (PGAML/PGAMR) PGAML/PGAMR configures the programmable-gain adjustment setting for the microphone left/microphone right input. Code 0x00 is maximum gain while 0x1F is maximum attenuation. Table 27 lists the gain setting for each code. Microphone Preamplifier Enable (PALEN/PAREN) 1 = Additional +20dB of gain applied to microphone inputs by the preamplifier 0 = 0dB of gain applied by the microphone preamplifier Preamplifier gain adds to the gain set by PGAML/ PGAMR. See the Microphone Amplifiers section.
MAX9851/MAX9853
Table 27. Microphone Input Gain Control Settings
PGAML/PGAMR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A SETTING (dB) +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 PGAML/PGAMR 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14-0x1F SETTING (dB) +9 +8 +7 +6 +5 +4 +3 +2 +1 +0
Microphone Control Register (0x12)
Table 28. Microphone Control Bit Settings
REG 0x12 B7 0 B6 0 B5 0 B4 0 B3 MMIC B2 MEXT B1 RBEN B0 RBIAS
Microphone Mute (MMIC) 1 = Mute all microphone inputs. 0 = Mute disabled. External Microphone Mode (MEXT) 1 = External microphone inputs. 0 = Internal microphone inputs.
Resistor Bias Enable (RBEN) 1 = Internal bias resistors for EXTMICBIASL and EXTMICBIASR connected. 0 = Internal bias resistors disconnected. Microphone Bias Output Impedance Select (RBIAS) 1 = 470. 0 = 2.2k. Select 2.2k when using electret or amplified microphones. Select 470 when using an external RC filter near the headset jack.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Audio Volume Control Registers (0x13, 0x14, 0x15, 0x16, 0x17)
Table 29. Sidetone Gain Bit Descriptions
REG 0x13 B7 0 B6 0 B5 0 B4 B3 B2 PGAS B1 B0
Sidetone Volume Control (PGAS) PGAS configures the volume of the sidetone signal that feeds into the audio output mixer. As the sidetone signal is routed from the left microphone input, this volume
control is in addition to the gain setting of the left microphone input. Code 0x00 is maximum gain while 0x1F is maximum attenuation. Table 30 lists the gain setting for each code.
Table 30. Sidetone Volume Control Settings
PGAS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F SETTING (dB) +30 +28 +26 +24 +22 +20 +18 +16 +14 +12 +10 +8 +6 +4 +2 0 PGAS 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F SETTING (dB) -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 -22 -24 -26 -28 -30 -32
Table 31. Headphone/Receiver Gain Bit Descriptions
REG 0x14 0x15 B7 0 0 B6 HRMUT 0 B5 B4 B3 HRVOLL HRVOLR B2 B1 B0
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Left and Right Headphone/Receiver Volume Control (HRVOLL/HRVOLR) HRVOLL/HRVOLR configure the volume of the left/right headphone output. HRVOLL and HRVOLR also control the volume of the receiver output as the receiver signal is a mono mix of both the left and the right headphone signals. Code 0x00 is maximum gain while 0x3F is full attenuation. Table 32 lists the gain setting for each code.
MAX9851/MAX9853
Table 32. Headphone/Receiver Volume Control Settings
HRVOLL/HRVOLR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 SETTING (dB) +5.5 +5.0 +4.5 +4.0 +3.5 +3.0 +2.5 +2.0 +1.0 0 -1.0 -2.0 -4.0 -6.0 -8.0 -10.0 -12.0 -14.0 -16.0 -18.0 -20.0 HRVOLL/HRVOLR 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 to 0x3F -- SETTING (dB) -22.0 -24.0 -26.0 -28.0 -30.0 -32.0 -34.0 -36.0 -38.0 -40.0 -42.0 -46.0 -50.0 -54.0 -58.0 -62.0 -66.0 -70.0 -74.0 Mute --
Headphone Mute (HRMUT) 1 = Headphone/receiver output muted. 0 = Headphone/receiver output level set by the volume control bits.
Table 33. Speaker/Line Out Gain Bit Descriptions
REG 0x16 0x17 B7 0 0 B6 SPMUT LOMUT2 0
1
B5
B4
B3
B2 SPVOLL LOPGAL2 SPVOLR1 LOPGAR2
1
B1
B0
1MAX9851. 2MAX9853
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
MAX9851: Left and Right Class D Volume Control (SPVOLL/SPVOLR) SPVOLL/SPVOLR configure the output volume of the MAX9851 left/right Class D speaker amplifier. Code 0x00 is maximum gain while 0x3F is full attenuation. Table 34 lists the gain setting for each code.
Table 34. Speaker Volume Control Settings
SPVOLL/SPVOLR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 SETTING (dB) +13.1 +12.6 +12.1 +11.6 +11.1 +10.6 +10.1 +9.6 +8.6 +7.6 +6.6 +5.6 +3.6 +1.6 -0.4 -2.4 -4.4 -6.4 -8.4 -10.4 -12.4 SPVOLL/SPVOLR 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 to 0x3F -- SETTING (dB) -14.4 -16.4 -18.4 -20.4 -22.4 -24.4 -26.4 -28.4 -30.4 -32.4 -34.4 -38.4 -42.4 -46.4 -50.4 -54.4 -58.4 -62.4 -66.4 Mute --
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
MAX9853: Left and Right Line Output Volume Control (LOPGAL/LOPGAR) LOPGAL/LOPGAR configures the output volume of the MAX9853 left/right differential line outputs. Code 0x00 is maximum gain while 0x3F is full attenuation. Table 35 lists the gain setting for each code. MAX9851: Speaker Output Mute (SPMUT) 1 = Speaker output muted. 0 = Speaker set by the volume control bits. MAX9853: Line Output Mute (LOMUT) 1 = Line output muted. 0 = Line output set by the volume control bits.
MAX9851/MAX9853
Table 35. Line Output Volume Control Settings
LOPGAL/LOPGAR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 SETTING (dB) +7.1 +6.6 +6.1 +5.6 +5.1 +4.6 +4.1 +3.6 +2.6 +1.6 +0.6 -0.4 -2.4 -4.4 -6.4 -8.4 -10.4 -12.4 -14.4 -16.4 -18.4 LOPGAL/LOPGAR 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 to 0x3F -- SETTING (dB) -20.4 -22.4 -24.4 -26.4 -28.4 -30.4 -32.4 -34.4 -36.4 -38.4 -40.4 -44.4 -48.4 -52.4 -56.4 -60.4 -64.4 -68.4 -72.4 Mute --
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Audio Output Control Register (0x18)
Table 36. Audio Output Bit Descriptions
REG 0x18
1
B7 0
B6 VSEN
B5 ZDEN
B4 SPMODE1 LOMODE2
B3
B2
B1 HRMODE
B0
MAX9851, 2MAX9853
Volume Adjustment Smoothing (VSEN) 1 = Volume changes smoothed by stepping through intermediate values. 0 = Volume changes made by bypassing intermediate settings. Zero-Crossing Detection (ZDEN) 1 = Volume changes made only at zero crossings in the audio waveform or after approximately 100ms. 0 = Volume changes made immediately upon request. MAX9851: Speaker Output Mode (SPMODE) 00 = Speaker amplifiers shutdown. 01 = Right channel enabled only. 10 = Left channel enabled only. 11 = Stereo speaker output enabled.
MAX9853: Line Output Mode (LOMODE) 00 = Line outputs disabled and SHDNOUT high. 11 = Line outputs enabled and SHDNOUT low. Headphone and Receiver Output Mode (HRMODE) 000 = Headphone and receiver amplifiers shutdown. 001 to 011 = Reserved. 100 = Stereo headphone mode. 101 = Single-ended mono headphone mode (L+R). 110 = Balanced mono headphone mode (bridge-tied load output L+R). 111 = Receiver amplifier enabled (L+R). HRMODE selects between headphone amplifier and receiver amplifier modes. The headphone amplifier and receiver amplifier cannot be enabled at the same time. To minimize click/pop, HRMODE should be programmed after power-on sequence and AOK = 1 (register 0x01, bit B7).
Vibe Gain and Headset Autodetect Register (0x19)
Table 37. Vibe and Headset Autodetect Bit Descriptions
REG 0x19 B7 B6 TGAIN B5 B4 B3 ENA B2 SLEEP B1 HSTEST B0
Transducer/Vibe Gain (TGAIN) TGAIN selects the programmable-gain setting of the VIBE signal data when signal conditioning is enabled.
Table 38 lists the gain setting for each code.
Table 38. Transducer DAC Gain Settings
TGAIN 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 T-DAC VIBE SIGNAL INPUT PGA Disabled, PGA output = 0 Reserved Reserved -30dB -24dB -18dB -12dB -6dB TGAIN 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF T-DAC VIBE SIGNAL INPUT PGA 0dB +6dB +12dB +18dB +24dB +30dB Reserved Reserved
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Headset Detect Enable (ENA) 1 = Enabled. 0 = Disabled. ENA = 1 enables the headphone sense biases and powers on the threshold comparator circuitry. Headphone amplifiers must be disabled and microphone amplifiers and bias resistors must be enabled for proper headset detection. ENA = 0 powers down the circuitry and sets HSDET (register 0x01, bits B5-B0) to 0x00. Headset Detect Low-Power Mode (SLEEP) 1 = Enabled. 0 = Disabled. SLEEP = 1 places the detection circuitry in low-power mode and disables normal detect mode. This feature is most useful when operating the MAX9851/MAX9853 in low-power shutdown mode. EXTMICBIASL is monitored and a hardware interrupt is triggered when a load is detected. Exit sleep mode to clear the hardware interrupt. Sleep mode is automatically entered when AV DD is removed and the battery voltage (PVDD) is still present. See the Headset Detect section. Headset Detect Configuration (HSTEST) 00 = Headphone sense bias disconnected. 01 = Headphone sense test 1 (standard headphone detection). 10 = Headphone sense test 2 (balanced mono headphone detection). 11 = Reserved. Set HRMODE = 000 prior to headset detection to disable the headphone amplifiers.
MAX9851/MAX9853
System Control Register (0x1A)
Table 39. System Bit Descriptions
REG 0x1A B7 SHDN B6 HFEN B5 LFEN B4 CPEN B3 0 B2 1 B1 0 B0 CPCLK
S Shutdown (SHDN) 1 = MAX9851/MAX9853 operational. 0 = Complete shutdown. SDALL is an active-low shutdown bit that overrides all settings and places the entire MAX9851/MAX9853 in low-power shutdown. Clock Input Enable (HFEN) 1 = Enable. 0 = Disable. HFEN = 1 enables the MCLK input and allows all clock dependent circuitry to operate. Analog Low-Frequency Oscillator Enable (LFEN) 1 = Enable. 0 = Disable.
LFEN = 1 enables the analog internal low-frequency oscillator that is used by the charge pump when MCLK is disabled. Charge-Pump Enable (CPEN) 1 = Enable. 0 = Disable. Always program to 1 for proper operation. Charge-Pump Oscillator Select (CPCLK) 1 = Charge-pump oscillator derived from MCLK. 0 = Charge-pump oscillator derived from internal oscillator. CPCLK = 1 configures the charge pump to use MCLK as a clock source. CPCLK = 0 configures the internal oscillator to be used instead of the MCLK. CPCLK must bet set to 1 when the Class D amplifier is being used (MAX9851 only).
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Shutdown Control Register (0x1B)
Table 40. Shutdown Bit Descriptions (0x1B)
REG 0x1B B7 DACLEN B6 DACREN B5 ADCLEN B4 ADCREN B3 DATEN B2 0 B1 MICLEN B0 MICREN
Left and Right DAC Enable (DACLEN/DACREN) 1 = Enable. 0 = Disable. Enable and disable the DACs only when S1SDI and S2SDI (register 0x03 and 0x05, bit B6) are cleared and all soft-stop sequences have completed (indicated by the SLD bit in resister 0x00) to insure proper click-andpop suppression. Disable DACLEN/DACREN before making interface mode changes. Left and Right ADC Enable (ADCLEN/ADCREN) 1 = Enable. 0 = Disable. Disable ADCLEN/ADCREN before making interface mode changes. Transducer/Vibe DAC Enable (DATEN) 1 = Enable. 0 = Disable. VIBE goes to high impedance when the DATEN is disabled. Left and Right Microphone Enable (MICLEN/MICREN) 1 = Enable. 0 = Disable.
I2C Serial Interface
The MAX9851/MAX9853 feature an I2C/SMBusTM-compatible, 2-wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL
facilitate communication between the MAX9851/ MAX9853 and the master at clock rates up to 400kHz. Figure 10 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9851/MAX9853 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9851/MAX9853 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9851/MAX9853 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9851/MAX9853 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9851/MAX9853 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tHD, STA tBUF tHD, STA tSP tSU, STO
Figure 10. 2-Wire Interface Timing Diagram SMBus is a trademark of Intel Corp. 60 ______________________________________________________________________________________
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy. START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-tohigh transition on SDA while SCL is high (Figure 11). A START condition from the master signals the beginning of a transmission to the MAX9851/MAX9853. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9851/MAX9853 recognize a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The MAX9851/MAX9853 are preprogrammed with a slave address of 0x20 or 0010000. The address is defined as the 7 most significant bits (MSBs) followed by the read/write bit. Set the read/write bit to 1 to configure the MAX9851/MAX9853 to read mode. Set the read/write bit to 0 to configure the MAX9851/MAX9853 to write mode. The address is the first byte of information sent to the MAX9851/MAX9853 after the START condition. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9851/MAX9853 use to handshake receipt each byte of data when in write mode (see Figure 12). The MAX9851/MAX9853 pull down SDA during the entire master-generated ninth clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the ninth clock cycle to acknowledge receipt of data when the MAX9851/ MAX9853 are in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9851/ MAX9853, followed by a STOP condition.
MAX9851/MAX9853
S
Sr
P
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
SCL
1
2
8 NOT ACKNOWLEDGE
9
SDA
SDA ACKNOWLEDGE
Figure 11. START, STOP, and REPEATED START Conditions
Figure 12. Acknowledge
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Write Data Format A write to the MAX9851/MAX9853 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 13 illustrates the proper frame format for writing one byte of data to the MAX9851/MAX9853. Figure 14 illustrates the frame format for writing n-bytes of data to the MAX9851/MAX9853. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9851/ MAX9853. The MAX9851/MAX9853 acknowledge receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9851/MAX9853's internal register address pointer. The pointer tells the MAX9851/MAX9853 where to write the next byte of data. An acknowledge pulse is sent by the MAX9851/MAX9853 upon receipt of the address pointer data. The third byte sent to the MAX9851/MAX9853 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9851/MAX9853 signals receipt of the data byte. The address pointer auto increments to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 14 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition. Register addresses greater than 0x1B are reserved. Do not write to these addresses.
ACKNOWLEDGE FROM MAX9851/MAX9853 B7 ACKNOWLEDGE FROM MAX9851/MAX9853 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9851/MAX9853 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 13. Writing 1 Byte of Data to the MAX9851/MAX9853
ACKNOWLEDGE FROM MAX9851/ MAX9853 ACKNOWLEDGE FROM MAX9851/ MAX9853 S SLAVE ADDRESS R/W 0 ACKNOWLEDGE FROM MAX9851/ MAX9853 A REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0
ACKNOWLEDGE FROM MAX9851/ MAX9853 B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE 1 1 BYTE
A
DATA BYTE n 1 BYTE
A
P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 14. Writing n-Bytes of Data to the MAX9851/MAX9853
62
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9851/MAX9853 acknowledge receipt of its slave address by pulling SDA low during the ninth SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00. The first byte transmitted from the MAX9851/MAX9853 will be the contents of register 0x00. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from register 0x00 and subsequent reads will autoincrement the address pointer until the next STOP condition. The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9851/MAX9853's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9851/MAX9853 transmit the contents of the specified register. The address pointer auto-increments after transmitting the first byte. Attempting to read from register addresses higher than 0x1F results in repeated reads of 0x1F. Note that 0x1C to 0x1F are reserved registers. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 15 illustrates the frame format for reading one byte from the MAX9851/MAX9853. Figure 16 illustrates the frame format for reading multiple bytes from the MAX9851/ MAX9853.
MAX9851/MAX9853
ACKNOWLEDGE FROM MAX9851/ MAX9853 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9851/ MAX9853 REGISTER ADDRESS A
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9851/ MAX9853 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTO-INCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 15. Reading One Indexed Byte of Data from the MAX9851/MAX9853
ACKNOWLEDGE FROM MAX9851/ MAX9853 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9851/ MAX9853 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX9851/ MAX9853 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTO-INCREMENT INTERNAL REGISTER ADDRESS POINTER A
REPEATED START
Figure 16. Reading n-Bytes of Indexed Data from the MAX9851/MAX9853
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63
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Applications Information
Typical Operating Modes
The MAX9851/MAX9853 are capable of a wide variety of operating modes. To ease the process of determining the appropriate settings for a particular operating mode, several typical modes of operation are detailed below. Voiceband Playback and Voiceband Record Typical cellular phone operation requires both playback and record functions, and audio data to be sent and received with the cell-phone communications chipset. Table 41 lists an example of this configuration and Table 42 lists the corresponding register settings in the proper programming sequence.
Table 41. Example Voiceband Playback and Voiceband Record Configuration
* 13MHz MCLK * 8kHz voice mode for incoming and outgoing data * DAC and ADC enabled for mono data * Digital audio input and output on the primary digital audio
interface operating in slave mode
* Voice filter activated for both DAC and ADC * Audio output on receiver amplifier * Audio input on internal microphone input
Table 42. I2C Register Settings for Voiceband Playback and Record Voiceband Mode
REGISTER (hex) 0x00 0x01 0x02 Program 0x03 last for proper soft-start 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x00 0x00 0x00 0x30 0x20 0x00 0x20 0x90 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x14 Configure for slave mode Disable secondary digital audio interface No configuration necessary Configure for a 13MHz MCLK and voiceband filtering on both the ADC and DAC Route digital audio from the primary interface to the left DAC No configuration necessary Route the left microphone signal to the ADC Route the left DAC output to the receiver amplifier and enabled sidetone No configuration necessary No configuration necessary No configuration necessary No configuration necessary Configure the left microphone input for +20dB of gain, adjust as appropriate No configuration necessary Select the internal microphone interface and disable external microphone bias circuitry Sidetone PGA, adjust as necessary Configure left output gain to -20dB, adjust as necessary VALUE (hex) N/A N/A 0x00 Read-only status register Read-only status register No interrupts are enabled DESCRIPTION
64
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Table 42. I2C Register Settings for Voiceband Playback and Record Voiceband Mode (continued)
REGISTER (hex) 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x03 VALUE (hex) 0x00 0x00 0x00 0x67 0x00 0xD5 0xA2 0xCA No configuration necessary No configuration necessary No configuration necessary Enable volume smoothing and zero-crossing detection and select the receiver amplifier for output No configuration necessary Enable the MAX9851/MAX9853 and configure the charge-pump circuitry to run from MCLK Enable the left DAC, left ADC, and microphone interface Enable primary digital audio interface and configure for full-duplex operation at 8kHz voice mode DESCRIPTION
MAX9851/MAX9853
Stereo Audio Playback with the MAX9851 Speaker Amplifier Typical operation often requires audio playback of a digital source. Table 43 lists an example of this configuration and Table 44 lists the corresponding register settings in the proper programming sequence. An example configuration is to supply I2S stereo digital audio sampled at 48kHz to the secondary digital audio interface (S2). The audio is converted to analog and amplified by the speaker amplifiers of the MAX9851. This configuration will be set to run from a 13MHz MCLK and operate the MAX9851 as the digital audio master.
Table 43. Example Stereo Audio Playback Configuration
* * * * *
13MHz MCLK 48kHz sample rate for incoming data DAC enabled for stereo data Digital audio input on the secondary digital audio interface operating in master mode Audio output on the speaker amplifier
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65
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 44. I2C Register Settings for Stereo Audio Playback Mode
REGISTER (hex) 0x00 0x01 0x02 0x03 0x04 Program 0x05 last for proper soft-start 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x05 0x88 0x00 0x84 0x00 0x00 0x11 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0E 0x0E 0x78 0x00 0xD5 0xC0 0x49 Configure for master mode and I2S data format Configure for a 13MHz MCLK Route digital audio from the secondary interface to the DAC No configuration necessary No configuration necessary Route the DAC output to the speaker amplifier No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary Configure left-speaker output for -0.4dB of gain, adjust as necessary Configure right-speaker output for -0.4dB of gain, adjust as necessary Enable volume smoothing and zero-crossing detection and select the speaker amplifier for stereo operation No configuration necessary Enable the MAX9851/MAX9853, configure the charge-pump circuitry to run from MCLK Enable the left and right DAC Enable secondary interface to input data at 48kHz VALUE (hex) -- -- 0x00 0x00 0x00 Read-only status register Read-only status register No interrupts are enabled Disable primary digital audio interface No configuration necessary DESCRIPTION
66
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Stereo Audio Record To record audio samples, only the ADC and microphone interface are required. Table 45 lists an example of this configuration and Table 46 lists the corresponding register settings in the proper programming sequence.
MAX9851/MAX9853
Table 45. Example Stereo Audio Record Configuration
* 13MHz MCLK * 48kHz sample rate for recorded data * Output data routed through the secondary digital audio
interface operating in master mode
* ADC enabled for stereo record * Audio input on external microphone input using internal bias
Table 46. I2C Register Settings for Stereo Audio Record Mode
REGISTER (hex) 0x00 0x01 0x02 0x03 0x04 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 -- -- 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x21 0x00 0x00 0x00 0x00 0x00 0x00 0x00 VALUE (hex) Read-only status register Read-only status register No interrupt enables are set No configuration necessary No configuration necessary Configure for master mode Configure for a 13MHz MCLK No configuration necessary No configuration necessary Route the left and right microphone signals to the ADC No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary Configure the left microphone input for +20dB of gain, adjust as appropriate Configure the left microphone input for +20dB of gain, adjust as appropriate DESCRIPTION
Program 0x05 last for proper soft-start
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67
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Table 46. I2C Register Settings for Stereo Audio Record Mode (continued)
REGISTER (hex) 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x05 0x06 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xD5 0x33 0x89 VALUE (hex) DESCRIPTION Select the external microphone interface and enable the external microphone bias circuitry using 2.2k bias resistors. No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary No configuration necessary Enable the MAX9851/MAX9853 and configure the charge-pump circuitry to run from MCLK (charge pump required to set AOK = 1 and allow digital circuitry to operate) Enable the ADC and microphone interface Enable secondary digital audio interface and configure for output operation at 48kHz stereo audio mode
PC Board Layout and Bypassing
Proper layout and grounding are essential for optimum performance. Use large traces for the power-supply inputs and amplifier outputs to minimize losses due to parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding improves audio performance, minimizes crosstalk between channels, and prevents any switching noise from coupling into the audio signal. Connect AGND, DGND, CPGND, and PGND (MAX9851 only) together at a single point on the PC board using the star grounding technique. Route DGND, CPGND, and all traces that carry switching transients or digital signals separately from AGND and analog audio signal paths. Ground all components associated with the charge pump to CPGND (CPV SS bypassing and CPV DD bypassing). Connect all digital I/O termination to DGND including DVDD and DVDDS2 bypassing. Bypass both PVDD pins on the MAX9851 (Class D power supplies) to PGND. Bypass VREF, MBIAS, INTMICBIAS to a quiet analog ground (AGND).
Connect PVSS and SVSS together at the device and place the charge-pump capacitors as close to SVSS as possible. Ensure C2 is connected to CPGND and bypass CPVDD with 1F to CPGND. Place the bypass capacitors as close to the device as possible. The MAX9851/MAX9853 thin QFN package features an exposed thermal pad on its underside. This pad lowers the package's thermal resistance by providing a directheat conduction path from the die to the PC board. If possible, connect the exposed thermal pad to an electrically isolated, large pad of copper. If it cannot be left floating, connect it to AGND. An evaluation kit (EV kit) is available to provide example layouts for the MAX9851 and MAX9853. The EV kit allows quick setup of the MAX9851/MAX9853 and includes easy-to-use software allowing all internal registers to be controlled.
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Pin Configurations
SDOUTS2 SDOUTS1 LRCLKS2 LRCLKS1 BCLKS2 BCLKS1 SDINS2 SDINS1
MAX9851/MAX9853
TOP VIEW
DGND
DVDD
SDA
36 35 34 33 32 31 30 29 28 27 26 25 DVDDS2 MCLK VIBE IRQ EXTMICR EXTMICL AGND EXTMICGND INTMICP INTMICN INTMICBIAS EXTMICBIASR 37 38 39 40 41 42 43 44 45 46 47 48 1 EXTMICBIASL 2 PREG 3 PVDD 4 LSPK+ 5 LSPK6 PGND 7 RSPK8 RSPK+ 9 PVDD 10 11 12 MBIAS NREG REF 24 23 22 21 20 19 CPVDD C1P CPGND C1N PVSS REC SVSS HPR HPL AVDD LINEIN2 LINEIN1
MAX9851
SCL 18 17 16 15 14 13 SCL
THIN QFN 7mm x 7mm
SDOUTS2 SDOUTS1 LRCLKS2 LRCLKS1 BCLKS2 BCLKS1 SDINS1 DGND DVDD
SDINS2
36 35 34 33 32 31 30 29 28 27 26 25 DVDDS2 MCLK VIBE IRQ EXTMICR EXTMICL AGND EXTMICGND INTMICP INTMICN INTMICBIAS EXTMICBIASR 37 38 39 40 41 42 43 44 45 46 47 48 1 EXTMICBIASL 2 PREG 3 OUTL+ 4 OUTL5 SHDNOUT 6 FAULTIN 7 PVDD 8 OUTR9 OUTR+ 10 11 12 NREG REF MBIAS 24 23 22 21 20 19 CPVDD C1P CPGND C1N PVSS REC SVSS HPR HPL AVDD LINEIN2 LINEIN1
MAX9853
SDA
18 17 16 15 14 13
THIN QFN 7mm x 7mm 69
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Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs MAX9851/MAX9853
Selector Guide
PART MAX9851ETM MAX9853ETM SPEAKER AMPLIFIERS -- LINE OUTPUTS -- I2C SLAVE ADDRESS 0x20 0x20
Chip Information
MAX9851 TRANSISTOR COUNT: 348,122 MAX9853 TRANSISTOR COUNT: 345,688 PROCESS: BiCMOS
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
E E/2
DETAIL A
(NE-1) X e
k e D/2
D
(ND-1) X e
C L
D2
D2/2
b L E2/2 k
C L
E2
C L
C L
L e e
L
A1
A2
A
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
1
2
70
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32, 44, 48L QFN.EPS
Stereo Audio CODECs with Microphone, DirectDrive Headphones, Speaker Amplifiers, or Line Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX9851/MAX9853
PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
F
2
2
MAX9851/MAX9853 Package Code: T4877-3
Revision History
Pages changed at Rev 1: 1, 2, 3-25, 30, 68, 71
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 71 (c) 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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